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* mesa: save/restore texture matrix in meta codeBrian Paul2009-08-101-1/+20
| | | | Also, save/restore viewport and texture state in _mesa_meta_copy_pixels()
* mesa: for meta blit, check max texture size, use glCopyTexSubImage2D() when ↵Brian Paul2009-08-101-2/+27
| | | | possible
* mesa: initial meta implementation of glCopyPixels()Brian Paul2009-08-102-0/+166
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* mesa: remove debug flush callBrian Paul2009-08-101-2/+0
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* intel: add missing \n to fprintf()Brian Paul2009-08-101-1/+1
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* intel: use new _mesa_meta_blit_framebuffer() functionBrian Paul2009-08-102-69/+7
| | | | | The previous version of framebuffer blit was a quick hack. The new meta version works pretty well.
* mesa: new driver meta-ops moduleBrian Paul2009-08-102-0/+881
| | | | | | | | | | | | | | | | | Implement glClear() in terms of quad rendering, implement glBlitFramebuffer() in terms of glCopyTexImage2D + textured quad, etc. There have been several places in the drivers where we've implemented meta rendering similar to this. This is an effort to do it in a more portable and more efficient form. The _mesa_meta_begin/end() functions act like glPush/PopAttrib() but are lighter-weight. Plus, _mesa_meta_begin() resets GL state back to default values (texturing off, identity vertex transform, etc) so the meta drawing functions don't have to worry about it. For now only _mesa_mesa_blit_framebuffer() and _mesa_meta_clear() are implemented. glDrawPixels() and glCopyPixels() would be the next candidates.
* radeon_fbo: switch short to byte for 565Dave Airlie2009-08-101-1/+1
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* radeon: fix cut-n-paste in alphabits in fbo codeDave Airlie2009-08-101-1/+1
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* r600: looks like a typoDave Airlie2009-08-091-1/+1
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* r600: load per-pixel position into PS in order to use fragment.position.Cooper Yuan2009-08-091-0/+27
| | | | | This patch can fix /progs/fp/tri-depth, tri-depth2, tri-depthwrite, tri-depthwrite2 and point-position.
* Revert "i965: Disable texture tiling by default."Eric Anholt2009-08-071-1/+5
| | | | | | | This reverts commit b8e638d4895d2d342306bb6443a455f73903ce20. Now that the known hangs and misrendering issues are fixed, I'm ready to start encouraging it by default again.
* intel: Align region height as required for tiled regions.Eric Anholt2009-08-071-0/+5
| | | | | | | Otherwise, we would address beyond the end of our buffers. Fixes reliable GPU segfault with texture_tiling=true and oglconform shadow.c. Bug #22406.
* i965: Add a note justifying domain choice for the SF VP.Eric Anholt2009-08-071-0/+3
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* intel: Add some more safety asserts in the blit code.Eric Anholt2009-08-071-0/+3
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* i965: Replace the subroutine-skipping jump in VS with a NOP if it's a NOP.Eric Anholt2009-08-071-1/+5
| | | | | This showed a 1.9% (+/-.3%, n=3) improvement in OA performance with high geometry settings.
* radeon: correct fix for tiling with the legacy buildAlex Deucher2009-08-072-6/+6
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* intel: Fix googleearth by avoiding GL_VIEWPORT_BIT in meta clear push/popEric Anholt2009-08-071-2/+5
| | | | | | I have no idea why this fixes things, but being more efficient sounds good anyway. Fixes regression in 99d07d0f91ddd37926d08f4e7f10d55cac28d9a7 where most of the lit half of the world was not drawn.
* radeon: fix the build with older drm headersAlex Deucher2009-08-071-0/+6
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* dri: Fix problems with unitialized values in dri screen object.Pauli Nieminen2009-08-071-1/+1
| | | | | | This fixes crash in r200 KMS driver when pSAREA was set to 1 randomly because of memory wasn't cleared. Signed-off-by: Pauli Nieminen <[email protected]>
* i965: minor context commentsBrian Paul2009-08-071-1/+5
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* intel: minor context commentsBrian Paul2009-08-071-1/+5
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* intel: move blit call out of assert()Brian Paul2009-08-071-7/+9
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* intel: fix typo: s/softare/software/Brian Paul2009-08-071-2/+2
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* radeon: enable tiling fallbacks in 3D driver.Dave Airlie2009-08-073-1/+28
| | | | | Only really got good testing on r500 so far, need to enable in DDX and play some more.
* radeon span: add r200 depth/stencil span read/writingDave Airlie2009-08-071-13/+111
| | | | | | this should only really affect DRI2 since we mostly have a surface in DRI1. I don't think this is perfect yet, but it is a better start than nothing.
* r200: fix scissor emission for r200 under kmsDave Airlie2009-08-071-18/+24
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* mesa: IgnoresJakob Bornecrantz2009-08-061-0/+1
| | | | Got tired of seeing these files in git status all the time
* i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-08-053-1/+5
| | | | | | | | For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603.
* Merge branch 'mesa_7_5_branch'Brian Paul2009-08-051-0/+5
|\ | | | | | | | | | | Conflicts: src/mesa/main/state.c
| * intel: Fix inverted test for disabling flushing of front buffer output.Brian Paul2009-08-041-1/+1
| | | | | | | | | | | | | | | | | | | | The comment disagreed with the code, and nicely drew my eyes to what was going wrong. Bug #21774 (blender) Bug #21788 (readpix) (cherry picked from master, commit fd65418f600874b05f902b622078b40bc1abb24a)
| * intel: Wait on the last swapbuffers to complete before queuing a new one.Brian Paul2009-08-043-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | This fixes jerkiness in doom3 and other apps since the kernel change to throttle less absurdly, which led to a thundering herd of frames. Because this is a rather minimal fix, there is at least one downside: If the whole scene completes in one batchbuffer, we'll end up stalling the GPU. Thanks to Michel Dänzer for suggesting using glFlush to signal frame end instead of going to all the effort of adding a new DRI2 extension. (cherry picked from master, commit 0828579a658af01a64b5e699175dc9bbbedcd685)
* | r200: emit colorpitchDave Airlie2009-08-051-2/+2
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* | i965: Fix dangerous warning I let slip in.Eric Anholt2009-08-041-1/+1
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* | i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-08-041-1/+21
| | | | | | | | | | | | | | Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be useful for the looping code. Bug #18992
* | i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt2009-08-041-0/+13
| | | | | | | | | | Previously, we'd be branching based on whatever condition code happened to be laying around.
* | i965: Don't set pop_count in the reserved MBZ area of IF statements.Eric Anholt2009-08-041-1/+1
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* | i965: Print out ELSE and ENDIF src1 arguments like IF does.Eric Anholt2009-08-041-2/+2
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* | r200: fix off-by-one errors causing 6th texture unit to not workRoland Scheidegger2009-08-051-2/+2
| | | | | | | | | | both for normal and cube textures, this fixes demos/multiarb (with 6 enabled texture units) and fixes #23142.
* | r200: fix compiler warning (unused var)Roland Scheidegger2009-08-051-2/+0
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* | radeon: fix miptree comparison breakageRoland Scheidegger2009-08-051-1/+2
| | | | | | | | another case of image never matching miptree in case of compressed textures
* | intel: implement intelCompressedTexSubImage2DRoland Scheidegger2009-08-051-21/+44
| | | | | | | | | | similar to the radeon code. passes tests/texcompsub
* | intel: Add support for EXT_provoking_vertex.Eric Anholt2009-08-0411-24/+131
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* | i965: Spell "conditional" correctly.Eric Anholt2009-08-043-16/+16
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* | i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt2009-08-048-12/+47
| | | | | | | | | | I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out, and running intel-gen4disasm on it.
* | i965: Initial import of disasm code from intel-gen4asm.Eric Anholt2009-08-041-0/+901
| | | | | | | | | | There's a bunch of stuff from gen4asm and gpu-tools that we probably want to make into a library instead of cargo-culting it around.
* | i965: warning fixEric Anholt2009-08-041-1/+1
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* | i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-08-041-1/+5
| | | | | | | | Bug #20821
* | i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-08-031-0/+14
| | | | | | | | | | | | | | | | | | | | This avoids sending a bad buffer address to the GPU due to programmer error, and is permitted by the ARB_vbo spec. Note that we still have the opportunity to dereference past the end of the GPU, because we aren't clipping to a correct _MaxElement, but that appears to be harder than it should be. This gets us the 90% solution. Bug #19911.
* | i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-08-031-0/+11
| | | | | | | | | | | | See comment on Vertex URB Entry Read Length for VS_STATE. This, combined with the previous three commits, fixes #22945.
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