summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers
Commit message (Expand)AuthorAgeFilesLines
* mesa: save/restore texture matrix in meta codeBrian Paul2009-08-101-1/+20
* mesa: for meta blit, check max texture size, use glCopyTexSubImage2D() when p...Brian Paul2009-08-101-2/+27
* mesa: initial meta implementation of glCopyPixels()Brian Paul2009-08-102-0/+166
* mesa: remove debug flush callBrian Paul2009-08-101-2/+0
* intel: add missing \n to fprintf()Brian Paul2009-08-101-1/+1
* intel: use new _mesa_meta_blit_framebuffer() functionBrian Paul2009-08-102-69/+7
* mesa: new driver meta-ops moduleBrian Paul2009-08-102-0/+881
* radeon_fbo: switch short to byte for 565Dave Airlie2009-08-101-1/+1
* radeon: fix cut-n-paste in alphabits in fbo codeDave Airlie2009-08-101-1/+1
* r600: looks like a typoDave Airlie2009-08-091-1/+1
* r600: load per-pixel position into PS in order to use fragment.position.Cooper Yuan2009-08-091-0/+27
* Revert "i965: Disable texture tiling by default."Eric Anholt2009-08-071-1/+5
* intel: Align region height as required for tiled regions.Eric Anholt2009-08-071-0/+5
* i965: Add a note justifying domain choice for the SF VP.Eric Anholt2009-08-071-0/+3
* intel: Add some more safety asserts in the blit code.Eric Anholt2009-08-071-0/+3
* i965: Replace the subroutine-skipping jump in VS with a NOP if it's a NOP.Eric Anholt2009-08-071-1/+5
* radeon: correct fix for tiling with the legacy buildAlex Deucher2009-08-072-6/+6
* intel: Fix googleearth by avoiding GL_VIEWPORT_BIT in meta clear push/popEric Anholt2009-08-071-2/+5
* radeon: fix the build with older drm headersAlex Deucher2009-08-071-0/+6
* dri: Fix problems with unitialized values in dri screen object.Pauli Nieminen2009-08-071-1/+1
* i965: minor context commentsBrian Paul2009-08-071-1/+5
* intel: minor context commentsBrian Paul2009-08-071-1/+5
* intel: move blit call out of assert()Brian Paul2009-08-071-7/+9
* intel: fix typo: s/softare/software/Brian Paul2009-08-071-2/+2
* radeon: enable tiling fallbacks in 3D driver.Dave Airlie2009-08-073-1/+28
* radeon span: add r200 depth/stencil span read/writingDave Airlie2009-08-071-13/+111
* r200: fix scissor emission for r200 under kmsDave Airlie2009-08-071-18/+24
* mesa: IgnoresJakob Bornecrantz2009-08-061-0/+1
* i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-08-053-1/+5
* Merge branch 'mesa_7_5_branch'Brian Paul2009-08-051-0/+5
|\
| * intel: Fix inverted test for disabling flushing of front buffer output.Brian Paul2009-08-041-1/+1
| * intel: Wait on the last swapbuffers to complete before queuing a new one.Brian Paul2009-08-043-0/+28
* | r200: emit colorpitchDave Airlie2009-08-051-2/+2
* | i965: Fix dangerous warning I let slip in.Eric Anholt2009-08-041-1/+1
* | i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-08-041-1/+21
* | i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt2009-08-041-0/+13
* | i965: Don't set pop_count in the reserved MBZ area of IF statements.Eric Anholt2009-08-041-1/+1
* | i965: Print out ELSE and ENDIF src1 arguments like IF does.Eric Anholt2009-08-041-2/+2
* | r200: fix off-by-one errors causing 6th texture unit to not workRoland Scheidegger2009-08-051-2/+2
* | r200: fix compiler warning (unused var)Roland Scheidegger2009-08-051-2/+0
* | radeon: fix miptree comparison breakageRoland Scheidegger2009-08-051-1/+2
* | intel: implement intelCompressedTexSubImage2DRoland Scheidegger2009-08-051-21/+44
* | intel: Add support for EXT_provoking_vertex.Eric Anholt2009-08-0411-24/+131
* | i965: Spell "conditional" correctly.Eric Anholt2009-08-043-16/+16
* | i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt2009-08-048-12/+47
* | i965: Initial import of disasm code from intel-gen4asm.Eric Anholt2009-08-041-0/+901
* | i965: warning fixEric Anholt2009-08-041-1/+1
* | i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-08-041-1/+5
* | i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-08-031-0/+14
* | i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-08-031-0/+11
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-15 20:02:57 +0000