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* Merge branch 'mesa_7_5_branch'Brian Paul2009-05-182-8/+21
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| * r300: Make sure to drop current hardware state reference to texture objects.Michel Dänzer2009-05-142-8/+21
* | intel: Don't complain on falling back from PBO fastpaths.Eric Anholt2009-05-151-3/+3
* | i915: Fix 945 cube map layout for the small mipmaps along the bottom.Steinar H. Gunderson2009-05-151-2/+14
* | i915: Use Stencil.Enabled instead of Stencil._Enabled in DrawBuffers.Eric Anholt2009-05-151-1/+1
* | i915: Only use the new 945 cube layout for compressed textures.Eric Anholt2009-05-151-1/+4
* | i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt2009-05-141-8/+10
* | i965: Fix register allocation of GLSL fp inputs.Eric Anholt2009-05-144-13/+27
* | intel: Use FRONT_AND_BACK for StencilOp as well.Eric Anholt2009-05-141-1/+2
* | intel: Use GL_FRONT_AND_BACK for stencil clearing.Eric Anholt2009-05-141-1/+2
* | i965: fix 1D texture borders with GL_CLAMP_TO_BORDERRobert Ellison2009-05-141-0/+10
* | i965: send all warnings through _mesa_warning()Robert Ellison2009-05-141-1/+1
* | Merge branch 'mesa_7_5_branch'Brian Paul2009-05-131-1/+2
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| * intel: added null ptr checkBrian Paul2009-05-131-1/+2
* | intel: enable GL_APPLE_vertex_array_objectBrian Paul2009-05-131-0/+2
* | Merge branch 'mesa_7_5_branch'Brian Paul2009-05-133-29/+75
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| * intel: create a private gl_array_object for intel_clear_tris(), fix bug 21638Brian Paul2009-05-133-29/+75
| * Test either GL_FRONT_LEFT or GL_FRONT for front-buffer renderingIan Romanick2009-05-111-1/+2
* | i965: enable additional code in emit_fb_write()Brian Paul2009-05-121-11/+10
* | i965: increase BRW_EU_MAX_INSNBrian Paul2009-05-121-1/+1
* | i965: commentBrian Paul2009-05-121-0/+4
* | intel: Skip the DRI2 renderbuffer update when doing Viewport on an FBO.Eric Anholt2009-05-121-1/+1
* | intel: Map write-only buffer objects through the GTT when possible.Eric Anholt2009-05-122-2/+15
* | i915: Fix driver after HW glGenerateMipmap commit.Eric Anholt2009-05-121-0/+1
* | i965: handle extended swizzle terms (0,1) in get_src_reg()Brian Paul2009-05-111-0/+8
* | i965: improve debug loggingRobert Ellison2009-05-083-14/+86
* | i965: fix memory leak in context/renderbuffer region managementRobert Ellison2009-05-081-4/+60
* | i965: fix segfault on low memory conditionsRobert Ellison2009-05-081-0/+7
* | intel: Add a metaops version of glGenerateMipmapEXT/SGIS_generate_mipmaps.Eric Anholt2009-05-0810-76/+303
* | intel: Put the constant texcoords used in metaops into a vbo.Eric Anholt2009-05-085-40/+102
* | i965: const qualifiersBrian Paul2009-05-081-2/+2
* | i965: don't use GRF regs 126,127 for WM programsBrian Paul2009-05-082-5/+28
* | i965: relAddr local var (to make debug/test a little easier)Brian Paul2009-05-071-5/+6
* | i965: Remove bad constant buffer constant-reg-already-loaded optimization.Eric Anholt2009-05-061-13/+11
* | intel: Unmap buffers if needed at DeleteBuffer time.Eric Anholt2009-05-061-1/+10
* | i965: Remove the forced lack of caching for renderbuffer surface state.Eric Anholt2009-05-061-11/+8
* | i965: Remove _NEW_PROGRAM from brw_wm_surfaces setup dependencies.Eric Anholt2009-05-061-2/+1
* | i965: Split WM constant buffer update from other WM surfaces.Eric Anholt2009-05-065-90/+95
* | i965: Disentangle VS constant surface state from WM surface state.Eric Anholt2009-05-067-186/+255
* | i965: Don't create constant buffers if they won't be used.Eric Anholt2009-05-061-1/+17
* | mesa: in glReadBufer() set _NEW_BUFFERS, not _NEW_PIXELBrian Paul2009-05-015-5/+6
* | Test either GL_FRONT_LEFT or GL_FRONT for front-buffer renderingIan Romanick2009-05-011-1/+2
* | Merge branch 'const-buffer-changes'Brian Paul2009-05-0114-200/+350
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| * i965: #include prog_print.h to silence warningBrian Paul2009-04-271-0/+1
| * i965: only upload constant buffer data when we actually need the const bufferBrian Paul2009-04-276-17/+22
| * i965: rework GLSL/WM register allocationBrian Paul2009-04-242-48/+168
| * i965: disable debug printfBrian Paul2009-04-221-1/+1
| * i965: enable VS constant buffersBrian Paul2009-04-221-5/+9
| * i965: define BRW_MAX_GRFBrian Paul2009-04-221-0/+3
| * i965: remove old code to init surface-related cache IDsBrian Paul2009-04-221-14/+0
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