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* i965: Set the alternative floating point mode on gen6 VS and WM.Eric Anholt2010-12-163-0/+8
| | | | | | | This matches how we did the math instructions pre-gen6, though it applies to non-math as well. Fixes vp1-LIT test 2 (degenerate case: 0 ^ 0 -> 1)
* i915: Fix INTEL_DEBUG=wm segmentation faultShuang He2010-12-161-5/+5
| | | | The program should be disassembled after it's uploaded
* i965: Add support for using the BLT ring on gen6.Eric Anholt2010-12-138-56/+72
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* i965: Improve the hacks for ARB_fp scalar^scalar POW on gen6.Eric Anholt2010-12-131-36/+17
| | | | | | | | | | | | This is still awful, but my ability to care about reworking the old backend so we can just get a temporary value into a POW is awfully low since the new backend does this all sensibly. Fixes: fp1-LIT test 1 fp1-LIT test 3 (case x < 0) fp1-POW test (exponentiation) fp-lit-mask
* i965: Fix gl_FragCoord.z setup on gen6.Eric Anholt2010-12-131-2/+7
| | | | Fixes glsl-bug-22603.
* i956: Fix the old FP path fragment position setup on gen6.Eric Anholt2010-12-131-18/+20
| | | | Fixes fp-arb-fragment-coord-conventions-none
* i965: Fix ARL to work on gen6.Eric Anholt2010-12-131-1/+17
| | | | | | | RNDD isn't one of the instructions that can do conversion from execution type to destination type. Fixes glsl-vs-arrays-3.
* intel: Include stdbool so we can stop using GLboolean when we want to.Eric Anholt2010-12-132-14/+12
| | | | | This requires shuffling the driconf XML macros around, since they use true and false tokens expecting them to not get expanded to anything.
* r300/compiler: fix swizzle lowering with a presubtract source operandMarek Olšák2010-12-111-0/+1
| | | | | | | | | | | | If a source operand has a non-native swizzle (e.g. the KIL instruction cannot have a swizzle other than .xyzw), the lowering pass uses one or more MOV instructions to move the operand to an intermediate temporary with native swizzles. This commit fixes that the presubtract information was lost during the lowering. NOTE: This is a candidate for both the 7.9 and 7.10 branches.
* r300/compiler: fix LIT in VSMarek Olšák2010-12-111-1/+2
| | | | | | | | | | | This fixes broken rendering of trees in ETQW. The trees still disappear for an unknown reason when they are close. Broken since: 2ff9d4474bdf5f05852ad4963d0b597d20743678 r300/compiler: make lowering passes possibly use up to two less temps NOTE: This is a candidate for the 7.10 branch.
* i965: Put common info on converting MESA_FORMAT to BRW_FORMAT in a table.Eric Anholt2010-12-101-126/+42
| | | | | | There are exceptions to the table for depth texturing or rendering to not-quite-supported formats thanks to the non-orthogonal component selection for surface formats, but it's still a lot simpler.
* intel: Just use ChooseTextureFormat for renderbuffer format choice.Eric Anholt2010-12-101-52/+9
| | | | One less place to forget to put your new MESA_FORMAT support in.
* intel: Add a couple of helper functions to reduce rb code duplication.Eric Anholt2010-12-105-138/+78
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* intel: Add spans code for the ARB_texture_rg support.Eric Anholt2010-12-102-0/+154
| | | | | This starts spantmp2.h down the path of using MESA_FORMAT_* for specifying the format instead of the crazy GL format/type combo.
* mesa/meta: fix broken assertion, rename stack depth varBrian Paul2010-12-101-5/+7
| | | | | | | assert(current_save_state < MAX_META_OPS_DEPTH) did not compile. Rename current_save_state to SaveStackDepth to be more consistent with the style of the other fields.
* i965: support for two-sided lighting on SandybridgeXiang, Haihao2010-12-105-6/+72
| | | | | | VS places color attributes together so that SF unit can fetch the right attribute according to object orientation. This fixes light issue in mesa demo geartrain, projtex.
* meta: allow nested meta operationsXiang, Haihao2010-12-101-4/+10
| | | | | | _mesa_meta_CopyPixels results in nested meta operations on Sandybridge. Previoulsy the second meta operation overrides all states saved by the first meta function.
* i965: Add support for gen6 reladdr VS constant loading.Eric Anholt2010-12-092-11/+17
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* i965: Add support for gen6 constant-index constant loading.Eric Anholt2010-12-092-3/+9
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* intel: Set the swizzling for depth textures using the GL_RED depth mode.Eric Anholt2010-12-092-0/+8
| | | | Fixes depth-tex-modes-rg.
* intel: Use plain R8 and RG8 for COMPRESSED_RED and COMPRESSED_RG.Eric Anholt2010-12-091-0/+2
| | | | Fixes texture-rg.
* i965: Silence uninitialized variable warning.Vinson Lee2010-12-091-0/+5
| | | | | | Fixes this GCC warning. brw_fs.cpp: In function 'brw_reg brw_reg_from_fs_reg(fs_reg*)': brw_fs.cpp:3255: warning: 'brw_reg' may be used uninitialized in this function
* i965: remove unused variable since brw_wm_glsl.c removal.Eric Anholt2010-12-092-2/+1
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* i965: Set render_cache_read_write surface state bit on gen6 constant surfs.Eric Anholt2010-12-092-0/+9
| | | | This is said to be required in the spec, even when you aren't doing writes.
* i965: Set up the correct texture border color state struct for Ironlake.Eric Anholt2010-12-092-5/+45
| | | | | This doesn't actually fix border color on Ironlake, but it appears to be a requirement, and gen6 needs it too.
* i965: Clean up VS constant buffer location setup.Eric Anholt2010-12-091-15/+3
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* i965: Fix VS constants regression pre-gen6.Eric Anholt2010-12-091-1/+1
| | | | Last minute change for gen6 with 0 used params dropped the multiply.
* i965: Drop push-mode reladdr constant loading and always use constant_map.Eric Anholt2010-12-084-93/+96
| | | | | | | | This eases the gen6 implementation, which can only handle up to 32 registers of constants, while likely not penalizing real apps using reladdr since all of those I've seen also end up hitting the pull constant buffer. On gen6, the constant map means that simple NV VPs fit under the 32-reg limit and now succeed. Fixes around 10 testcases.
* radeon: bump mip tree levels to 15Alex Deucher2010-12-091-1/+1
| | | | I forgot to bump this when I bumped the tex levels.
* i965: Drop KIL_NV from the ff/ARB_fp path since it was only used for GLSL.Eric Anholt2010-12-083-21/+0
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* i965: Use the new pixel mask location for gen6 ARB_fp KIL instructions.Eric Anholt2010-12-081-2/+8
| | | | | | Fixes: fp-kil fp-generic/kil-swizzle.
* i965: Set the render target index in gen6 fixed-function/ARB_fp path.Eric Anholt2010-12-081-0/+7
| | | | | | Fixes: fbo-drawbuffers2-blend fbo-drawbuffers2-colormask
* i965: Set up the per-render-target blend state on gen6.Eric Anholt2010-12-081-46/+49
| | | | This will let us get EXT_draw_buffers2 blending and colormasking working.
* i965: Set up the color masking for the first drawbuffer on gen6.Eric Anholt2010-12-081-0/+9
| | | | Fixes glean/maskedClear
* r300/compiler: remove at least unused immediates if externals cannot be removedMarek Olšák2010-12-083-8/+6
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* r300/compiler: make lowering passes possibly use up to two less tempsMarek Olšák2010-12-081-63/+86
| | | | | | | | | CMP may now use two less temps, other non-native instructions may end up using one less temp, except for SIN/COS/SCS, which I am leaving unchanged for now. This may reduce register pressure inside loops, because the register allocator doesn't do a very good job there.
* r300/compiler: handle DPH and XPD in rc_compute_sources_for_writemaskMarek Olšák2010-12-081-0/+5
| | | | This bug can only be triggered if you put deadcode before native rewrite.
* r300/compiler: do not print pair/tex/presub program stats for vertex shadersMarek Olšák2010-12-081-16/+30
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* r300/compiler: cleanup rc_run_compilerMarek Olšák2010-12-084-15/+36
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* r300/compiler: add a function to query program stats (alu, tex, temps..)Marek Olšák2010-12-082-15/+39
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* r300/compiler: don't terminate regalloc if we surpass max temps limitMarek Olšák2010-12-081-11/+6
| | | | The same check is already in a later pass (translate_vertex_program).
* i965: Don't try to store gen6 (float) blend constant color in bytes.Eric Anholt2010-12-071-1/+1
| | | | Fixes glean/blendFunc
* i965: Fix flipped value of the not-embedded-in-if on gen6.Eric Anholt2010-12-071-1/+1
| | | | | | Fixes: glean/glsl1-! (not) operator (1, fail) glean/glsl1-! (not) operator (1, pass)
* i965: Work around gen6 ignoring source modifiers on math instructions.Eric Anholt2010-12-073-3/+26
| | | | | | | | | | | | | | | With the change of extended math from having the arguments moved into mrfs and handed off through message passing to being directly hooked up to the EU, it looks like the piece for doing source modifiers (negate and abs) was left out. Fixes: fog-modes glean/fp1-ARB_fog_exp test glean/fp1-ARB_fog_exp2 test glean/fp1-Computed fog exp test glean/fp1-Computed fog exp2 test ext_fog_coord-modes
* i965: Add disabled debug code for dumping out the WM constant payload.Eric Anholt2010-12-071-0/+15
| | | | This can significantly ease thinking about the asm.
* i965: Correctly emit constants for aggregate types (array, matrix, struct)Ian Romanick2010-12-071-19/+61
| | | | | | | Previously the code only handled scalars and vectors. This new code is modeled somewhat after similar code in ir_to_mesa. Reviewed-by: Eric Anholt <[email protected]>
* i965: Always hand the absolute value to RSQ.Eric Anholt2010-12-072-1/+6
| | | | | | | | | | gen6 builtin RSQ apparently clamps negative values to 0 instead of returning the RSQ of the absolute value like ARB_fragment_program desires and pre-gen6 apparently does. Fixes: glean/fp1-RSQ test 2 (reciprocal square root of negative value) glean/vp1-RSQ test 2 (reciprocal square root of negative value)
* i965: Handle saturates on gen6 math instructions.Eric Anholt2010-12-071-0/+2
| | | | | | We get saturate as an argument to brw_math() instead of as compile state, since that's how the pre-gen6 send instructions work. Fixes fp-ex2-sat.
* i965: Fix comment about gen6_wm_constants.Eric Anholt2010-12-071-1/+1
| | | | This is the push constant buffer, not the pull constants.
* i965: upload WM state for _NEW_POLYGON on sandybridgeZhenyu Wang2010-12-071-1/+1
| | | | Be sure polygon stipple mode is updated. This fixes 'gamma' demo.
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