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* glsl: Allow vector logic ops to be generated.Matt Turner2015-03-241-6/+3
| | | | | | | They're not accessible from the source language, but optimizations are allowed to generate them. Reviewed-by: Ian Romanick <[email protected]>
* i965: add the remaining files to the tarballEmil Velikov2015-03-241-0/+3
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix handling of multiple register reads and writes in ↵Francisco Jerez2015-03-231-7/+15
| | | | | | dead_code_eliminate(). Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Calculate live intervals with subregister granularity.Francisco Jerez2015-03-232-33/+46
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Define helpers to calculate the common live interval of a range ↵Francisco Jerez2015-03-234-29/+31
| | | | | | | | | of variables. These will be especially useful when we start keeping track of liveness information for each subregister. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Define helper functions to convert a register to a variable index.Francisco Jerez2015-03-234-28/+34
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Don't lose the force_writemask_all flag during CSE.Francisco Jerez2015-03-231-0/+3
| | | | | | | And set it in the MOV instructions that copy the temporary to the original destination if the generator instruction had it set. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix handling of multiple register reads and writes in opt_cse().Francisco Jerez2015-03-231-8/+17
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix handling of multiple register reads and writes during copy ↵Francisco Jerez2015-03-231-3/+6
| | | | | | propagation. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix handling of multiple register reads and writes in ↵Francisco Jerez2015-03-231-9/+6
| | | | | | split_virtual_grfs(). Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix handling of multiple register reads and writes in ↵Francisco Jerez2015-03-231-14/+10
| | | | | | opt_register_coalesce(). Reviewed-by: Matt Turner <[email protected]>
* i965: Define method to check whether a backend_reg is inside a given range.Francisco Jerez2015-03-233-4/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Remove dependency of vec4_live_variables on the visitor.Francisco Jerez2015-03-232-7/+8
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Trivial copy propagate clean-up.Francisco Jerez2015-03-231-5/+6
| | | | | | | Fix typo and punctuation in a comment, break long line and add space before curly bracket. Reviewed-by: Abdiel Janulgue <[email protected]>
* i965/vec4: Add argument index and type checks to SEL saturate propagation.Francisco Jerez2015-03-231-1/+4
| | | | | | | SEL saturate propagation already implicitly relies on these assumptions. Reviewed-by: Abdiel Janulgue <[email protected]>
* i965/vec4: Fix broken saturate mask check in copy propagation.Francisco Jerez2015-03-231-4/+11
| | | | | | | | | | | try_copy_propagate() was checking the bit of the saturate mask for the arg-th component of the source to decide whether the whole source should be saturated (WTF?). We need to swizzle the original saturate mask and check that for all enabled channels the saturate flag is either set or unset, as we cannot saturate a subset of destination components only. Reviewed-by: Abdiel Janulgue <[email protected]>
* i965/vec4: Don't lose copy propagation saturate bits for not written components.Francisco Jerez2015-03-231-1/+1
| | | | Reviewed-by: Abdiel Janulgue <[email protected]>
* Revert "i965/vec4: Don't lose the saturate modifier in copy propagation."Francisco Jerez2015-03-231-1/+1
| | | | | | | | | This reverts commit 0dfec59a2785cf7a87ee5128889ecebe810b611b. The change prevented propagation of copies with the saturate flag set, making the whole saturate mask tracking completely useless. A proper fix follows. Reviewed-by: Abdiel Janulgue <[email protected]>
* i965/vec4: Remove unused method definition.Francisco Jerez2015-03-231-1/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Some more trivial swizzle clean-up.Francisco Jerez2015-03-235-30/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Improve src_reg/dst_reg conversion constructors.Francisco Jerez2015-03-231-26/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This simplifies the src_reg/dst_reg conversion constructors using the swizzle utils introduced in a previous patch. It also makes them more useful by changing their semantics slightly: dst_reg(src_reg) used to set the writemask to XYZW if the src_reg swizzle was anything other than XXXX, which was almost certainly not what the caller intended if the swizzle was non-trivial. After this patch the same components that are present in the swizzle will be enabled in the resulting writemask. src_reg(dst_reg) used to set the first components of the swizzle to the enabled components of the writemask and then replicate the last enabled component to fill the swizzle, which, in cases where the writemask didn't have exactly the first n components set, would in general not be compatible with the original dst_reg. E.g.: | ADD(tmp, src_reg(tmp), src_reg(1)); would *not* do what one would expect (add one to each of the enabled components of tmp) if tmp didn't have a writemask of the described form (e.g. YZ, YW, XZW would all fail). This pattern actually occurs in many different places in the VEC4 back-end, it's a wonder that it hasn't caused piglit failures until now. After this patch src_reg(dst_reg) will construct a swizzle with each enabled component at its natural position (e.g. Y at the second position, Z at the third, and so on). The resulting swizzle will behave like the identity when used in any instruction with the original writemask. I've manually verified that *none* of the callers of both conversion constructors were relying on the previous broken semantics. There are no piglit regressions on any generation. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Pass argument by reference to src_reg/dst_reg conversion ↵Francisco Jerez2015-03-232-4/+4
| | | | | | constructors. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Remove swizzle_for_size() in favour of brw_swizzle_for_size().Francisco Jerez2015-03-233-31/+8
| | | | | | | | | | It could be objected that swizzle_for_size() is "faster" than brw_swizzle_for_size(). It's not measurably better in any reasonable CPU-bound benchmark on VLV according to the Finnish benchmarking system (including the SynMark2 DrvShComp shader compilation benchmark). Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Remove broken vector size deduction in ↵Francisco Jerez2015-03-231-14/+9
| | | | | | | | | | | setup_builtin_uniform_values(). This seemed to be trying to deduce the number of uniform vector components from the parameter swizzle, but the algorithm would always give 4 as result. Instead grab the correct number of components from the GLSL type. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Simplify visitor handling of swizzles using the swizzle utils.Francisco Jerez2015-03-231-49/+10
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Simplify opt_register_coalesce() using the swizzle utils.Francisco Jerez2015-03-231-26/+7
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Simplify reswizzle() using the swizzle utils.Francisco Jerez2015-03-231-29/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Simplify opt_reduce_swizzle() using the swizzle utils.Francisco Jerez2015-03-231-44/+7
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Fix signedness of backend_reg::reg_offset.Francisco Jerez2015-03-231-1/+1
| | | | | | And make it 16-bit so it packs nicely with the previous field. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix signedness of dst_reg::writemask.Francisco Jerez2015-03-232-3/+4
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Don't use GL types in the IR data structures.Francisco Jerez2015-03-231-1/+1
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix signedness of brw_is_single_value_swizzle() argument.Francisco Jerez2015-03-231-1/+1
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Define some useful swizzle helper functions.Francisco Jerez2015-03-231-0/+97
| | | | | | | | | | This defines helper functions implementing some common swizzle transformations that are usually open-coded in the compiler back-end, causing a lot of clutter. Some optimization passes will become almost trivial implemented in terms of these functions (e.g. vec4_visitor::opt_reduce_swizzle()). Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Use signed integer type for booleansJason Ekstrand2015-03-231-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FS instructions with NIR on i965: total instructions in shared programs: 2663561 -> 2619051 (-1.67%) instructions in affected programs: 1612965 -> 1568455 (-2.76%) helped: 5455 HURT: 12 FS instructions with NIR on g4x: total instructions in shared programs: 2352633 -> 2307908 (-1.90%) instructions in affected programs: 1441842 -> 1397117 (-3.10%) helped: 5463 HURT: 11 FS instructions with NIR on ilk: total instructions in shared programs: 3997305 -> 3934278 (-1.58%) instructions in affected programs: 2189409 -> 2126382 (-2.88%) helped: 8969 HURT: 22 FS instructions with NIR on hsw (snb and ivb were similar): total instructions in shared programs: 4109389 -> 4109242 (-0.00%) instructions in affected programs: 109869 -> 109722 (-0.13%) helped: 339 HURT: 190 No SIMD16 programs were gained or lost on any platform Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Do boolean resolves on GEN <= 5Jason Ekstrand2015-03-231-0/+20
| | | | | | v2: A couple comment clean-ups from Matt Reviewed-by: Matt Turner <[email protected]>
* i965: Add a NIR analysis pass for determining when a boolean resolve is neededJason Ekstrand2015-03-233-0/+348
| | | | | | | | | | v2: Fix the spelling of analyze and re-arrange code for better readability as per Connor's comments. v3: Make the naming of things more consistent and add a pile of comments v4: Stop trying to avoid vectors Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965/nir: Properly set the predicate on the SEL used in min/maxJason Ekstrand2015-03-231-0/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Use NIR lowering for ffma for gen < 6Jason Ekstrand2015-03-231-2/+10
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Use emit_lrp for emitting flrpJason Ekstrand2015-03-231-2/+1
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Make emit_lrp return an fs_instJason Ekstrand2015-03-232-5/+5
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: define I915_PARAM_REVISIONDave Airlie2015-03-231-0/+5
| | | | | | | we are broken against the libdrm 2.4.60 minimum specified, so fix it for now. Signed-off-by: Dave Airlie <[email protected]>
* i965/fs: Use correct null destination register in cmod testsIan Romanick2015-03-201-3/+3
| | | | | | | Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89670 Reviewed-by: Matt Turner <[email protected]> Cc: Vinson Lee <[email protected]>
* i965/fs: bail on move-to-flag in sel peepholeConnor Abbott2015-03-201-1/+3
| | | | | | | | | Fixes a piglit regression (shaders/glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined) with my series for GVN. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Connor Abbott <[email protected]>
* i965: Mask out unused Align16 components in brw_untyped_atomic.Francisco Jerez2015-03-201-2/+11
| | | | | | | | | | | | This is currently not a problem because the vec4 visitor happens to mask out unused components from the destination, but it might become an issue when we start using atomics without writeback message. In any case it seems sensible to set it again here because the consequences of setting the wrong writemask (random graphics memory corruption) are difficult to debug and can easily go unnoticed. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Pass number of components explicitly to brw_untyped_atomic and ↵Francisco Jerez2015-03-204-16/+32
| | | | | | | | | | | | _surface_read. And calculate the message response size based on the number of components rather than the other way around. This simplifies their interface somewhat and allows the caller to request a writeback message with more than one vector component in SIMD4x2 mode. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Don't disable exec masking for sampler message sends.Francisco Jerez2015-03-202-8/+8
| | | | | | | | | | This was telling the sampler to do texture fetches for *all* channels in the non-constant surface index case, what could have reduced throughput unnecessarily when some of the channels were disabled by control flow. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Factor out logic to build a send message instruction with indirect ↵Francisco Jerez2015-03-204-96/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | descriptor. This is going to be useful because the Gen7+ uniform and varying pull constant, texturing, typed and untyped surface read, write, and atomic generation code on the vec4 and fs back-end all require the same logic to handle conditionally indirect surface indices. In pseudocode: | if (surface.file == BRW_IMMEDIATE_VALUE) { | inst = brw_SEND(p, dst, payload); | set_descriptor_control_bits(inst, surface, ...); | } else { | inst = brw_OR(p, addr, surface, 0); | set_descriptor_control_bits(inst, ...); | inst = brw_SEND(p, dst, payload); | set_indirect_send_descriptor(inst, addr); | } This patch abstracts out this frequently recurring pattern so we can now write: | inst = brw_send_indirect_message(p, sfid, dst, payload, surface) | set_descriptor_control_bits(inst, ...); without worrying about handling the immediate and indirect surface index cases explicitly. v2: Rebase. Improve documentatation and commit message. (Topi) Preserve UW destination type cargo-cult. (Topi, Ken, Matt) Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Set nr_params to the number of uniform components in the VS/GS path.Francisco Jerez2015-03-203-15/+4
| | | | | | | | | | | | | | | | | | Both do_vs_prog and do_gs_prog initialize brw_stage_prog_data::nr_params to the number of uniform *vectors* required by the shader rather than the number of uniform components, contradicting the comment. This is inconsistent with what the state upload code and scalar path expect but it happens to work until Gen8 because vec4_visitor interprets it as a number of vectors on construction and later on overwrites its original value with the number of uniform components referenced by the shader. Also there's no need to add the number of samplers, they're not actually passed in as uniforms. Fixes a memory corruption issue on BDW with SIMD8 VS. Cc: "10.5" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/skl: Break down SIMD16 3-source instructions when required.Kenneth Graunke2015-03-201-0/+6
| | | | | | | | | | | | | Several steppings of Skylake fail when using SIMD16 with 3-source instructions (such as MAD). This implements WaDisableSIMD16On3SrcInstr and fixes ~190 Piglit tests. Based on a patch by Neil Roberts. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Refactor SIMD16-to-2xSIMD8 checks.Neil Roberts2015-03-201-4/+14
| | | | | | | | | | | The places that were checking whether 3-source instructions are supported have now been combined into a small helper function. This will be used in the next patch to add an additonal restriction. Based on a patch by Kenneth Graunke. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
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