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* i965: Ensure that all 2101010 image imports can pass framebuffer completeness.Miguel Casas-Sanchez2019-11-191-2/+6
| | | | | | | | | | | Chrome OS would like to import and render to any supported format that has a corresponding display plane format, and this prevents throwing framebuffer incomplete for FBOs using these textures. See: crbug.com/949260 Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* Call shmget() with permission 0600 instead of 0777Brian Paul2019-11-181-1/+2
| | | | | | | | | | | | | | A security advisory (TALOS-2019-0857/CVE-2019-5068) found that creating shared memory regions with permission mode 0777 could allow any user to access that memory. Several Mesa drivers use shared- memory XImages to implement back buffers for improved performance. This path changes the shmget() calls to use 0600 (user r/w). Tested with legacy Xlib driver and llvmpipe. Cc: [email protected] Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel/compiler: Add a flag to avoid compacting push constantsJason Ekstrand2019-11-181-0/+1
| | | | | | | In vec4, we can just not run the pass. In fs, things are a bit more deeply intertwined. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Unify CC_STATE and BLEND_STATE atoms on Haswell as a workaroundDanylo Piliaiev2019-11-181-2/+35
| | | | | | | | | | | | | | | | | | | Re-emitting 3DSTATE_CC_STATE_POINTERS after emitting 3DSTATE_BLEND_STATE_POINTERS fixes the shadow flickering in SuperTuxCart and Tropico 6 which was seen only on Haswell. The reason for this is unknown and fix was found empirically. The closest mention in PRM is that it should improve performance. From the HSW PRM, volume 2b, page 823 (3DSTATE_BLEND_STATE_POINTERS): "When the BLEND_STATE pointer changes but not the CC_STATE pointer, driver needs to force a CC_STATE pointer change to improve blend performance in pixel backend." Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1834 Fixes: eca4a654 ("i965: Disable dual source blending when shader doesn't support it on gen8+") Cc: <[email protected]> Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/program_cache: Lift restriction on shader key sizeDanylo Piliaiev2019-11-121-12/+4
| | | | | | | | This will allow usage of packed structs which may have size not divisible by 4. Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* Meson: Remove lib prefix from graw and osmesa when building with Mingw.Prodea Alexandru-Liviu2019-11-071-0/+2
| | | | | | | | | | | Also remove version sufix from osmesa swrast on Windows. v2: Make sure we don't remove lib prefix on *nix platforms. Signed-off-by: Prodea Alexandru-Liviu <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Cc: "19.3" <[email protected]>
* mesa: Prepare for the MESA_FORMAT_* enum to be sparse.Eric Anholt2019-11-071-0/+2
| | | | | | | | | To redefine MESA_FORMAT in terms of PIPE_FORMAT enums, we need to fix places where we iterated up to MESA_FORMAT_COUNT. I use _mesa_get_format_name(f) == NULL as the signal that it's not an enum value with a MESA_FORMAT. Reviewed-by: Marek Olšák <[email protected]>
* util: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIANDylan Baker2019-11-057-14/+14
| | | | | | | | | | | As requested by Tim. This was generated with: grep 'PIPE_ARCH_.*_ENDIAN' -rIl | xargs sed -ie 's@PIPE_ARCH_\(.*\)_ENDIAN@UTIL_ARCH_\1_ENDIAN@'g v2: - add this patch Reviewed-by: Eric Engestrom <[email protected]>
* util/u_endian: set PIPE_ARCH_*_ENDIAN to 1Dylan Baker2019-11-057-14/+14
| | | | | | | | | | | | This will allow it to be used as a drop in replacement for _mesa_little_endian in a number of cases. v2: - Always define PIPE_ARCH_LITTLE_ENDIAN and PIPE_ARCH_BIG_ENDIAN, define the one that reflects the host system to 1 and the other to 0 - replace all uses of #ifdef, #ifndef, and #if defined() with #if and #if ! with PIPE_ARCH_*_ENDIAN Reviewed-by: Eric Engestrom <[email protected]>
* dri/osmesa: use preprocessor for selecting endian code pathsDylan Baker2019-11-051-6/+9
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* r100: Use preprocessor to select big vs little endian pathsDylan Baker2019-11-053-46/+51
| | | | Reviewed-by: Eric Engestrom <[email protected]>
* r200: use preprocessor for big vs little endian checksDylan Baker2019-11-052-45/+38
| | | | | | | Instead of using a function at runtime we can just build the right code for the right platform. Reviewed-by: Eric Engestrom <[email protected]>
* radeon: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* r200: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* nouveau: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* i915: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* dri: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* intel: Support HIZ_CCS in isl_surf_get_ccs_surfNanley Chery2019-10-282-8/+8
| | | | | | | Add an extra aux parameter which will be filled out with CCS if the first two isl_surf parameters fit the requirements for HiZ_CCS. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Avoid -Wswitch for the Gen12 aux modesNanley Chery2019-10-281-0/+3
| | | | | | | | Avoid the compiler warnings for the new enums that will be introduced in a future commit. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* util: rename list_empty() to list_is_empty()Timothy Arceri2019-10-281-1/+1
| | | | | | | This makes it clear that it's a boolean test and not an action (eg. "empty the list"). Reviewed-by: Eric Engestrom <[email protected]>
* i965: setup sized internalformat for MESA_FORMAT_R10G10B10A2_UNORMTapani Pälli2019-10-281-1/+9
| | | | | | | | | | | | | | | Commit d2b60e433e5 introduced restrictions (as per GLES spec) on the internal format. We need to setup a sized format for the texture image so framebuffers created with that are considered complete. This change fixes following Android CTS test in AHardwareBufferNativeTests category: SingleLayer_ColorTest_GpuColorOutputAndSampledImage_R10G10B10A2_UNORM Signed-off-by: Tapani Pälli <[email protected]> Fixes: d2b60e433e5 ("mesa/main: R10G10B10_(A2) formats are not color renderable in ES") Reviewed-by: Kenneth Graunke <[email protected]>
* intel/perf: move registers to their own headerLionel Landwerlin2019-10-232-1/+2
| | | | | | | Will conflict with the genxml RPSTAT register. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* mesa: Redefine the RG formats as array formats.Eric Anholt2019-10-203-10/+10
| | | | | | | | | This is the layout used in the GL API, and maps directly to PIPE formats with no endianness trickery. As with the LA change, this fixes big-endian fetching from texbos. Also cleans up some endian shenanigans in shader images. Reviewed-by: Marek Olšák <[email protected]>
* mesa: Replace MESA_FORMAT_L8A8/A8L8 UNORM/SNORM/SRGB with an array format.Eric Anholt2019-10-2010-27/+18
| | | | | | | | | | | | | | | | | The array format is what the GL API wants (fixing texbos on big-endian), and matches directly to gallium's corresponding array format. The only driver exposing A8L8 was radeon/r200 in big-endian, where the HW's underlying format was trying to read as array and we needed to flip things around to make our packed format come out right (note that while the radeon format tables had both AL and LA, ChooseTextureFormat would only pick one of them based on endianness). v2: Don't make r200/radeon use endian swaps. v3: Rebase on dropping the r200 _be/_le format table removal patch v4: reword commit message to explain why we can drop both formats from radeon. Reviewed-by: Marek Olšák <[email protected]> (v1)
* mesa: Replace the LA16_UNORM packed formats with one array format.Eric Anholt2019-10-202-2/+5
| | | | | | | | | | | The array format is what the GL API wants (and we made a mistake in the format returned for texbos on big-endian!), and it's exactly what the gallium-side PIPE_FORMAT_L16A16 is. The only downside is that dri_util tries to fall back to sampling RG16 using LA16, which doesn't have a match for big-endian any more. No HW drivers supported A16L16 anyway. Reviewed-by: Marek Olšák <[email protected]>
* radeon: Drop the unused first arg of OUT_BATCH_RELOC.Eric Anholt2019-10-209-24/+24
| | | | | | | This was a trap when trying to figure out how to fit data bits into the reloc. Reviewed-by: Marek Olšák <[email protected]>
* radeon: Fill in the TXOFFSET field containing the tile bits in our relocs.Eric Anholt2019-10-202-4/+5
| | | | | | | | | | The first arg to OUT_BATCH_RELOC is ignored, we actually wanted these in the third arg. They're always 0 so far, so it didn't matter. v2: Reword commit message that I don't end up using the tile bits, but keep the commit as a cleanup anyway. Reviewed-by: Marek Olšák <[email protected]> (v1)
* r100/r200: factor out txformat/txfilter setup from the TFP path.Eric Anholt2019-10-202-22/+10
| | | | | | | | | No matter what, we deref the texFormat from the table, except for a mistake in cpp=4 where we pulled a 0 out of the table either way. v2: Rebase on dropping r200 table deduplication patch. Reviewed-by: Marek Olšák <[email protected]> (v1)
* Revert "egl: Fixes transparency with EGL and X11."Hal Gentz2019-10-181-2/+0
| | | | This reverts commit 90a19074b4e1d4d8f8ababaade8170c05aeecffe.
* nir: support feeding state to nir_lower_clip_[vg]sErik Faye-Lund2019-10-171-1/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* nir: support lowering clipdist to arraysErik Faye-Lund2019-10-171-1/+1
| | | | | | | | This allows us to make sure clipdist is emitted as a scalar array rather than two vec4s. This matches SPIR-V semantics, and will be useful for Zink. Reviewed-by: Marek Olšák <[email protected]>
* egl: Fixes transparency with EGL and X11.Hal Gentz2019-10-111-0/+2
| | | | | | | | | | | | | This commit does this by allowing both RGB and RGBA visuals to match with EGL configs. We also expose the `EGL_MESA_config_select_group` egl extension, which is similar to GLX's visual select group extension, to allow the RGBA visuals to get less priority. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67676 Fixes: 049f343e8ac "egl: Allow 24-bit visuals for 32-bit RGBA8888 configs" Cc: [email protected] Reviewed-by: Adam Jackson <[email protected]> Signed-off-by: Hal Gentz <[email protected]>
* GL: drop symbols mangling supportEric Engestrom2019-10-102-8/+0
| | | | | | | | | | SCons and Meson have never supported that feature, and Autotools was deleted over 6 months ago and no-one complained yet, so it's pretty obvious nobody cares about it. Fixes: 95aefc94a941701616fd ("Delete autotools") Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* nir: add a strip parameter to nir_serializeMarek Olšák2019-10-101-1/+1
| | | | | | | so that drivers don't have to call nir_strip manually. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* i965: Disable fast clears when running with INTEL_DEBUG=nofcCaio Marcelo de Oliveira Filho2019-10-092-0/+6
| | | | Reviewed-by: Rafael Antognolli <[email protected]>
* meta: leak of shader program when decompressing tex-imagesSergii Romantsov2019-10-091-0/+1
| | | | | | CC: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Sergii Romantsov <[email protected]>
* i965: Enable EXT_demote_to_helper_invocationCaio Marcelo de Oliveira Filho2019-09-301-0/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Increase Gen11 compute shader scratch IDs to 64.Kenneth Graunke2019-09-231-1/+13
| | | | | | | | | | | | | | | | | | | | | | | From the MEDIA_VFE_STATE docs: "Starting with this configuration, the Maximum Number of Threads must be set to (#EU * 8) for GPGPU dispatches. Although there are only 7 threads per EU in the configuration, the FFTID is calculated as if there are 8 threads per EU, which in turn requires a larger amount of Scratch Space to be allocated by the driver." It's pretty clear that we need to increase this for scratch address calculations, because the FFTID has a certain bit-pattern. The quote above seems to indicate that we should increase the actual thread count programmed in MEDIA_VFE_STATE as well, but we think the intention is to only bump the scratch space. Fixes GPU hangs in Bioshock Infinite and Synmark's CSDof on Icelake 8x8. Fixes: 5ac804bd9ac ("intel: Add a preliminary device for Ice Lake") Reviewed-by: Matt Turner <[email protected]>
* Revert "intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM"Kenneth Graunke2019-09-232-9/+0
| | | | | | | | | | | | | | | This reverts commit 729de1488f49033bc181b8123af5658228a51bf1. It turns out that, although the register is in the logical context, it isn't whitelisted, so we can't actually write it from userspace batch buffers. The write just becomes a noop, which is why we saw no performance changes. I manually whitelisted it, and still observed no performance gains, but it did regress KHR-GL46.texture_cube_map_array.color_depth_attachments on the iris driver. So we might need to fix something before enabling this. To prevent it randomly getting turned on should the kernel ever whitelist this register, we revert the patch for now.
* Move blob from compiler/ to util/Jason Ekstrand2019-09-191-1/+1
| | | | | | | | There's nothing whatsoever compiler-specific about it other than that's currently where it's used. Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: support AYUV/XYUV for external import onlyHaihao Xiang2019-09-181-0/+2
| | | | | | | | | Fixes: 89785e2d56e7fa ("i965: add support for sampling from AYUV") Fixes: 7cab8d3661f243 ("i965: Add support for sampling from XYUV images") Cc: Vivek Kasireddy <[email protected]> Cc: Lionel Landwerlin <[email protected]> Signed-off-by: Haihao Xiang <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* scons: Make scons and meson agree about path to glapi generated headersDylan Baker2019-09-163-1/+3
| | | | | | | | Currently scons puts them in src/mapi/glapi, meosn puts them in src/mapi/glapi/gen. This results in some things being compilable only by one or the other, put them in the same places so that everyone is happy. Reviewed-by: Eric Engestrom <[email protected]>
* driconfig: add a new engine name/version parameterLionel Landwerlin2019-09-156-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vulkan applications can register with the following structure : typedef struct VkApplicationInfo { VkStructureType sType; const void* pNext; const char* pApplicationName; uint32_t applicationVersion; const char* pEngineName; uint32_t engineVersion; uint32_t apiVersion; } VkApplicationInfo; This enables the Vulkan implementations to apply workarounds based off matching this description. Here we add a new parameter for matching the driconfig options with the following : <device driver="anv"> <application engine_name_match="MyOwnEngine.*" engine_versions="10:12,40:42"> <option name="blaaah" value="true" /> </application> </device> v2: switch engine name match to use regexps v3: Verify that the regexec returns REG_NOMATCH for match failure (Eric) v4: Add missing bit that went to the following commit (Eric) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: 19.2 <[email protected]>
* dri: Use DRM_FORMAT_* instead of defining our own copy.Eric Anholt2019-09-112-46/+47
| | | | | | | | | | | | We have only two defines that aren't from DRM_FORMAT_*: SARGB and SABGR. Keep only those as __DRI_IMAGE_FOURCC and garbage collect the rest. While this header is also used from the X server, the X server doesn't use any __DRI_IMAGE enums. Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WMAnuj Phogat2019-09-112-0/+9
| | | | | | | Initial benchmarking didn't show any performance benefits. But it might eventually. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl/nir: Add and use a gl_nir_link() functionCaio Marcelo de Oliveira Filho2019-09-101-8/+4
| | | | | | | | | Perform all the NIR linking steps in order. Change iris and i965 to use it. Suggested by Alejandro. v2: Add gl_nir_linker_options struct. Reviewed-by: Alejandro Piñeiro <[email protected]> [v1]
* glsl/nir: Fill in the Parameters in NIR linkerCaio Marcelo de Oliveira Filho2019-09-101-1/+1
| | | | | | | | | | | | | | | | | | | | | The parameter lists were not being created nor filled since i965 doesn't use them. In Gallium they are used for uniform handling, so add a way to fill them. The gl_uniform_storage struct got two new fields that let us go - from a Parameter to the matching UniformStorage and, - from the variable to the *first* UniformStorage without relying on names -- since they are optional for ARB_gl_spirv. Later patches will make use of them. v2: Do not fill parameters for i965. (Timothy) Use uint32_t for the new attributes. (Marek) v3: Serialize the new fields. (Timothy) Reviewed-by: Timothy Arceri <[email protected]>
* mesa: Eliminate gl_config::rgbModeAdam Jackson2019-09-092-16/+3
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: Eliminate gl_config::have{Accum,Depth,Stencil}BufferAdam Jackson2019-09-095-20/+12
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: Remove unused gl_config::indexBitsAdam Jackson2019-09-091-1/+0
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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