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* intel: Fix uninitialized values in debug output for renderbuffer mapping.Eric Anholt2011-12-141-1/+1
* radeon: stop using _DepthBuffer, _StencilBuffer fieldsBrian Paul2011-12-132-9/+8
* nouveau: stop using _DepthBuffer, _StencilBuffer fieldsBrian Paul2011-12-136-13/+14
* mesa,intel: use _mesa_image_offset() for PBOsnobled2011-12-081-2/+3
* mesa/drivers: use new swrast renderbuffer functionsBrian Paul2011-12-0812-62/+74
* mesa: rewrite accum buffer supportBrian Paul2011-12-082-2/+3
* mesa: remove the ctx->Driver.IsTextureResident() hookBrian Paul2011-12-081-1/+0
* mesa: remove TextureMemCpy driver hookBrian Paul2011-12-081-1/+0
* i965 gen6: Implement pass-through GS for transform feedback.Paul Berry2011-12-076-46/+208
* i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.Paul Berry2011-12-075-24/+59
* i965 gs: Clean up dodgy register re-use, at the cost of a few MOVs.Paul Berry2011-12-072-65/+111
* i965 gen6: Allocate URB space for GSPaul Berry2011-12-073-12/+63
* i965: Set the maximum number of GS URB entries on Sandybridge.Kenneth Graunke2011-12-071-0/+2
* i965: Only convert if/else to conditional adds prior to Gen6.Paul Berry2011-12-071-2/+28
* i965 gs: Remove unnecessary mapping of key->primitive.Paul Berry2011-12-072-16/+7
* i965: Set Ivybridge's is_array SURFACE_STATE bit.Kenneth Graunke2011-12-071-1/+2
* i965: Return BRW_DEPTHBUFFER_D32_FLOAT as the null-depthbuffer format.Kenneth Graunke2011-12-071-0/+3
* intel: Update comment about how depth/stencil miptrees are handled.Eric Anholt2011-12-071-6/+18
* intel: Rely on miptree mapping for all renderbuffer maps.Eric Anholt2011-12-072-202/+21
* intel: Add support for LLC-cached reads of X-tiled miptrees using a blit.Eric Anholt2011-12-072-0/+83
* intel: Handle MapRenderbuffer of fake packed depth/stencil using miptree maps.Eric Anholt2011-12-071-138/+2
* intel: Track miptrees for fake packed depth/stencil renderbuffers.Eric Anholt2011-12-071-0/+10
* intel: Make the fake packed depth/stencil mappings use a cached temporary.Eric Anholt2011-12-072-121/+129
* intel: Make intel_region_map return void *.Eric Anholt2011-12-072-4/+4
* intel: Move separate-stencil s8 mapping logic to intel_miptree_map.Eric Anholt2011-12-072-113/+112
* intel: Move the gtt-particular texture mapping logic to a helper function.Eric Anholt2011-12-071-49/+71
* intel: Make mapping of texture slices track the region of interest.Eric Anholt2011-12-072-5/+51
* intel: Move the teximage mapping logic to a miptree level/slice mapping.Eric Anholt2011-12-073-48/+109
* intel: Only prefer separate stencil when we can do HiZ.Eric Anholt2011-12-072-4/+14
* i965: Set SURFACE_STATE vertical alignment bit on Ivybridge.Kenneth Graunke2011-12-061-0/+7
* radeon: add original r100 to the always tiled depth list.Dave Airlie2011-12-061-1/+1
* osmesa: remove unused bpc variableFabio Pedretti2011-12-061-8/+0
* radeon/r200: add RV200 detiling + add an always tiled flagDave Airlie2011-12-063-37/+72
* r200: add Z16 depth detiling.Dave Airlie2011-12-061-0/+105
* r200: handle Z24 depth buffers correctlyDave Airlie2011-12-061-2/+2
* r200: fix cb microtile setupDave Airlie2011-12-061-0/+3
* r200: enable tiling flags on blitter setup.Dave Airlie2011-12-061-0/+10
* i965: Fix incorrect comment about single program flow on Ironlake.Kenneth Graunke2011-12-051-1/+1
* radeon/r200: drop old span depth/stencil code.Dave Airlie2011-12-051-317/+0
* radeon/r200: add draw/stencil buffer detilingDave Airlie2011-12-052-0/+111
* radeon: fix warningsDave Airlie2011-12-051-2/+2
* radeon: use mesa renderbuffer accessors for depth for now.Dave Airlie2011-12-051-4/+5
* radeon: add some tiling support for r100.Dave Airlie2011-12-052-0/+13
* radeon: texture/renderbuffer overhaul.Dave Airlie2011-12-0513-599/+385
* radeon: set texture bits to always emit.Dave Airlie2011-12-051-3/+3
* radeon: update flush according to glXMakeCurrent man pageDave Airlie2011-12-051-2/+15
* radeon: drop border checkDave Airlie2011-12-051-5/+0
* radeon: add a bit more debugging to the blit debug code.Dave Airlie2011-12-051-4/+4
* i965: Fix emit of a MOV with bad destination channel on gen6 math in FPs.Stuart Abercrombie2011-12-021-5/+5
* mesa: rename MESA_FORMAT_RG88_REV to MESA_FORMAT_RG88Brian Paul2011-12-021-1/+1
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