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* blorp: Pass the batch to lookup/upload_shader instead of contextKenneth Graunke2019-01-101-4/+4
| | | | | | | | | This will allow drivers to pin shader buffers if necessary. i965 and anv do not need to do this today, but iris will. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* blorp: Add blorp_get_surface_address to the driver interface.Kenneth Graunke2019-01-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, BLORP expects drivers to provide two functions for dealing with buffers: blorp_emit_reloc and blorp_surface_reloc. Both record a relocation and combine the BO address and offset into a full 64-bit address. Traditionally, blorp_surface_reloc has written that combined address to an implicitly-known buffer where surface states are stored. (In contrast, blorp_emit_reloc returns the value.) The upcoming Iris driver stores surface states in multiple buffers, which makes it impossible for blorp_surface_reloc to write the combined address - it only takes an offset, not the actual buffer to write to. This commit adds a third function, blorp_get_surface_address, which combines and returns an address, which is then passed to ISL's surface state fill functions. Softpin-only drivers can return a real address here and skip writing it in blorp_surface_reloc. Relocation-based drivers are have options. They can simply return 0 from the new function, and continue writing the address from blorp_surface_reloc. Or, they can return a presumed address from blorp_get_surface_address, and have other relocation processing write the real value later. For now, i965 and anv simply return 0. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Compile fp64 funcs only if we do not have 64-bit hardware supportMatt Turner2019-01-101-1/+1
| | | | Brown bag fix...
* intel/isl: move tiled_memcpy static libs from i965 to islTapani Pälli2019-01-1014-1459/+91
| | | | | | | | | | | | | | Patch moves intel_tiled_memcpy[_sse41] libraries to isl, renames some functions and types and makes the required build system changes for meson, automake and Android. No functional changes are introduced. v2: code cleanups, move isl_get_memcpy_type to i965 (Jason) v3: move isl_mem_copy_fn to priv header, cleanups (Jason, Dylan) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Enable 64-bit GLSL extensionsMatt Turner2019-01-091-4/+4
| | | | | | | Now that we have software implementations of ARB_gpu_shader_int64 and ARB_gpu_shader_fp64 we can unconditionally enable these extensions. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Compile fp64 software routines and lower double-opsMatt Turner2019-01-093-1/+63
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Create file to contain software fp64 functionsMatt Turner2019-01-091-0/+1
| | | | | | | The following patches will add implementations of various double-precision operations to this file. Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: fix printf format specifier.Maya Rashish2019-01-091-1/+1
| | | | | | | | | | | | From glibc printf(3): Z A nonstandard synonym for z that predates the appearance of z. Do not use in new code. Z may not exist on non-glibc systems. Prefer the standard symbol. Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* spirv: Sort supported capabilitiesJason Ekstrand2019-01-071-5/+5
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* i965: add CS stall on VF invalidation workaroundLionel Landwerlin2019-01-042-2/+2
| | | | | | | | | | | | | | | | | | | Even with the previous commit, hangs are still happening. The problem there is that the VF cache invalidate do happen immediately without waiting for previous rendering to complete. What happens is that we invalidate the cache the moment the PIPE_CONTROL is parsed but we still have old rendering in the pipe which continues to pull data into the cache with the old high address bits. The later rendering with the new high address bits then doesn't have the clean cache that it expects/needs. v2: Update commit message/explanation with Jason's Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Fixes: a363bb2cd0e2a1 ("i965: Allocate VMA in userspace for full-PPGTT systems.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072
* i965: include draw_params/derived_draw_params for VF cache workaroundLionel Landwerlin2019-01-041-5/+18
| | | | | | | | | | | These buffers are using VB slots and should be included in the workaround decision. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Fixes: a363bb2cd0e2a1 ("i965: Allocate VMA in userspace for full-PPGTT systems.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109072
* i965: limit VF caching workaround to gen8/9/10Lionel Landwerlin2019-01-042-2/+4
| | | | | | | | | Documentation of the 3DSTATE_VERTEX_BUFFERS packet says this is only needed before ICL. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't override subslice count to 4 on Gen11.Kenneth Graunke2018-12-171-1/+1
| | | | | | | | Gen9-10 have fewer than 4 subslices per slice, so they need this to be rounded up. Gen11 isn't documented as needing this hack, and it can also have more than 4 subslices, so the hack actually can break things. Reviewed-by: Anuj Phogat <[email protected]>
* i965/gen9: Add workarounds for object preemption.Rafael Antognolli2018-12-141-0/+63
| | | | | | | | | | | | | | | | | | | | | Gen9 hardware requires some workarounds to disable preemption depending on the type of primitive being emitted. We implement this by adding a function that checks the primitive type and number of instances right before the 3DPRIMITIVE. For now, we just ignore blorp. The only primitive it emits is 3DPRIM_RECTLIST, and since it's not listed in the workarounds, we can safely leave preemption enabled when it happens. Or it will be disabled by a previous 3DPRIMITIVE, which should be fine too. v3: - Apply missing workarounds for instanced rendering and line loop (Ken) - Move workaround code to brw_draw_single_prim() Signed-off-by: Rafael Antognolli <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen10+: Enable object level preemption.Rafael Antognolli2018-12-144-1/+36
| | | | | | | | | | | | Set bit when initializing context. v3: - Always toggle preemption bool to false before enabling it for the first time, so the state gets emitted (Chris Wilson). - Emit end of pipe sync with PIPE_CONTROL_RENDER_TARGET_FLUSH (Ken) Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke2018-12-141-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* i965/compute: Emit GPGPU_WALKER in genX_state_uploadJordan Justen2018-12-123-130/+105
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/genX_state: Add register access functionsJordan Justen2018-12-121-0/+31
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Flip arguments to load_register_reg helpers.Kenneth Graunke2018-12-095-9/+10
| | | | | | | | | load_register_imm and load_register_mem take the destination as the first argument, so I'd like load_register_reg to do the same the sake of consistency. Otherwise, reading sequences of mixed LRI/LRM/LRR is needlessly confusing. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Delete dead brw_meta_resolve_color prototype.Kenneth Graunke2018-12-091-7/+0
| | | | Dead since commit 09e041d61d367ff3a9e8492521606090050255d4 (May 2016).
* intel/blorp: Expand blorp_address::offset to be 64 bits.Kenneth Graunke2018-12-073-3/+3
| | | | | | | | | | | | | In the softpin world, surface state base address may be a fixed 64-bit address (with no associated BO). It makes sense to store this in the offset field. But it needs to be the full size. We also update the clear color address to be consistently uint64_t everywhere so we can continue passing intel_miptree_get_clear_color a pointer to the blorp_address's offset field without type mismatches. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* mesa: Add core support for EXT_multisampled_render_to_texture{,2}Kristian H. Kristensen2018-12-061-1/+1
| | | | | | | | | This also turns on EXT_multisampled_render_to_texture which is a subset of EXT_multisampled_render_to_texture2, allowing only COLOR_ATTACHMENT0. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kristian H. Kristensen <[email protected]>
* mesa: Revert INTEL_fragment_shader_ordering supportMatt Turner2018-12-031-1/+0
| | | | | | | | | | | | | | | | This extension is not properly tested (testing for GL_ARB_fragment_shader_interlock is not sufficient), and since this was noted in review on August 28th no tests have been sent. Revert "i965: Add INTEL_fragment_shader_ordering support." Revert "mesa: Add GL/GLSL plumbing for INTEL_fragment_shader_ordering" This reverts commit 03ecec9ed2099f6e2b62994b33dc948dc731e7b8. This reverts commit 119435c8778dd26cb7c8bcde9f04b3982239fe60. Cc: [email protected] Acked-by: Jason Ekstrand <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965: Fix -Wswitch on INTEL_COPY_STREAMING_LOADChad Versace2018-12-031-1/+3
| | | | | | | The warning is emitted when building without INLINE_SSE41. Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Set the FBO error state INCOMPLETE_ATTACHMENT only for SRGB_R8Gert Wollny2018-11-281-3/+10
| | | | | | | | | | | | | | | Originally the driver reported GL_FRAMEBUFFER_UNSUPPORTED in all cases, adding more specific error messages was not correct and broke many tests. Mostly revert this and only report GL_FRAMEBUFFER_INCOMPLETE_ATTACHMENT for MESA_FORMAT_R_SRGB8. Fixes: ebcde3454552adc6d3fea8af2207aafaba857796 i965: be more specific about FBO completeness errors Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108805 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Explicitely handle swizzles for MESA_FORMAT_R_SRGB8Gert Wollny2018-11-281-3/+7
| | | | | | | | | | | | The format is emulated by using ISL_FORMAT_L8_SRGB, therefore we need to force swizzles for the GBA channels. However, doing this only based on the data type GL_RED breaks other formats, therefore, test specifically for the format. Fixes: c5363869d4971780401b21bb75083ef2518c12be i965: Force zero swizzles for unused components in GL_RED and GL_RG Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965/icl: Set use full ways in L3CNTLREGAnuj Phogat2018-11-262-0/+2
| | | | | | | | L3 allocation table in h/w specification recommends using 4 KB granularity for programming allocation fields in L3CNTLREG. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* mesa: Factor out struct gl_vertex_format.Mathias Fröhlich2018-11-215-49/+51
| | | | | | | | | | | | | | | | Factor out struct gl_vertex_format from array attributes. The data type is supposed to describe the type of a vertex element. At this current stage the data type is only used with the VAO, but actually is useful in various other places. Due to the bitfields being used, special care needs to be taken for the glGet code paths. v2: Change unsigned char -> GLubyte. Use struct assignment for struct gl_vertex_format. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* nouveau: Use gl_array_attribute::_ElementSize.Mathias Fröhlich2018-11-211-1/+1
| | | | | | | | | Instead of open coding the size computation, use the already available gl_array_attribute::_ElementSize value. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* i965: Do NIR shader cloning in the caller.Kenneth Graunke2018-11-206-6/+7
| | | | | | | | | | | | This moves nir_shader_clone() to the driver-specific compile function, rather than the shared src/intel/compiler code. This allows i965 to do key-specific passes before calling brw_compile_*. Vulkan should not need this cloning as it doesn't compile multiple variants. We do need to continue cloning in the compute shader code because we lower various things in NIR based on the SIMD width. Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: Use a 'nir' temporary rather than poking at brw_programKenneth Graunke2018-11-206-22/+25
| | | | | | It's shorter and will also be useful when I adjust cloning soon. Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965/batch: avoid reverting batch buffer if saved state is an emptyAndrii Simiklit2018-11-205-2/+13
| | | | | | | | | | | | | | | | | | | | | There's no point reverting to the last saved point if that save point is the empty batch, we will just repeat ourselves. v2: Merge with new commits, changes was minimized, added the 'fixes' tag v3: Added in to patch series v4: Fixed the regression which was introduced by this patch Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630 Reported-by: Mark Janes <[email protected]> The solution provided by: Jordan Justen <[email protected]> CC: Chris Wilson <[email protected]> Fixes: 3faf56ffbdeb "intel: Add an interface for saving/restoring the batchbuffer state." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107626 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630 (fixed in v4) Signed-off-by: Andrii Simiklit <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965:use FRAMEBUFFER_UNSUPPORTED instead of FRAMEBUFFER_INCOMPLETE_DIMENSIONSGert Wollny2018-11-191-1/+1
| | | | | | | | | | | | | | FRAMEBUFFER_INCOMPLETE_DIMENSIONS is not supported for GLES 3.0 and later and not defined for Desktop OpenGL. Instead use FRAMEBUFFER_UNSUPPORTED like it was done before. Thanks to Iago Toral and Andrey Simiklit for pointing out the problem and the details. Fixes: ebcde3454552adc6d3fea8af2207aafaba857796 i965: be more specific about FBO completeness errors Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Add support for and expose EXT_texture_sRGB_R8Gert Wollny2018-11-192-0/+2
| | | | | | | | | | | | | | Emulate MESA_FORMAT_R_SRGB8 by using L8_UNORM_SRGB. This is possible because component swizzling is handled based on the mesa format and, hence, the a r001 swizzling can be used to correct the components. Enables and makes pass (tested on Kabylake) dEQP-GLES31.functional.srgb_texture_decode.skip_decode.sr8.* dEQP-GLES31.functional.texture.filtering.cube_array.formats.sr8* Signed-off-by: Gert Wollny <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* i965: Force zero swizzles for unused components in GL_RED and GL_RGGert Wollny2018-11-191-0/+4
| | | | | | | This makes it possible to use a hardware luminance format as RED format. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: be more specific about FBO completeness errorsGert Wollny2018-11-191-19/+23
| | | | | | | | | | | The driver was returning GL_FRAMEBUFFER_UNSUPPORTED for all cases of an incomplete fbo, be a bit more specific about this following the description of glCheckFramebufferStatus. This helps to keeps dEQP happy when adding EXT_texture_sRGB_R8 support. Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i915: Delete swizzling detection logic.Kenneth Graunke2018-11-174-31/+0
| | | | | | | This is all leftover from the i965 split. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Fix calculation of layers array length for isl_viewDanylo Piliaiev2018-11-151-15/+18
| | | | | | | | | | | | | | | | | | | | | | | Handle all cases in calculation of layers count for isl_view taking into account texture view and image unit. st_convert_image was taken as a reference. When u->Layered is true the whole level is taken with respect to image view. In other case only one layer is taken. v3: (Józef Kucia and Ilia Mirkin) - Rewrote patch by taking st_convert_image as a reference - Removed now unused get_image_num_layers function - Changed commit message v4: (Jason Ekstrand) - Added assert Fixes: 5a8c8903 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107856 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: avoid 'unused variable' warningsAndrii Simiklit2018-11-142-3/+3
| | | | | | | | | | | | | | 1. brw_pipe_control.c:311:34: warning: unused variable ‘devinfo’ 2. brw_program_binary.c:209:19: warning: unused variable ‘gen_size’ 3. brw_program_binary.c:216:19: warning: unused variable ‘nir_size’ v2: Changes for unreproducible issues were removed Signed-off-by: Andrii Simiklit <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: add support for sampling from AYUVLionel Landwerlin2018-11-122-0/+9
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Lift restriction in external textures for EGLImage supportAditya Swarup2018-11-083-15/+0
| | | | | | | | | | | | | | | | Fixes Skqp's unitTest_EGLImageTest test. For Intel platforms, we support external textures only for EGLImages created with EGL_EXT_image_dma_buf_import. This restriction seems to be Intel specific and not present for other platforms. While running SKQP test - unitTest_EGLImageTest, GL_INVALID is sent to the test because of this restriction. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105301 Signed-off-by: Aditya Swarup <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/batch/debug: Allow log be dumped before assertSergii Romantsov2018-11-051-1/+1
| | | | | | | | | Message that may show the culprit of assert now will be dumped before that for debug purposes. Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Lionel G Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/icl: Disable prefetching of sampler state entriesTopi Pohjolainen2018-11-021-3/+12
| | | | | | | | | | | | | | | | | | | In the same spirit as commit a5889d70f2074201ceaeac4f96a9a0c0b1f68a31 "i965/icl: Disable binding table prefetching". Fixes some 110+ intermittent piglit failures with tex-miplevel-selection variants. WA_1606682166: Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes. Disable the Sampler state prefetch functionality in the SARB by programming 0xB000[30] to '1'. This is to be done at boot time and the feature must remain disabled permanently. Anuj: Set SamplerCount = 0 for vs, gs, hs, ds and wm units as well. Signed-off-by: Topi Pohjolainen <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Cc: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "i965/batch: avoid reverting batch buffer if saved state is an empty"Mark Janes2018-11-015-14/+3
| | | | | | This reverts commit a9031bf9b55602d93cccef6c926e2179c23205b4. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108630
* i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREGAnuj Phogat2018-11-012-0/+8
| | | | | | | | The default setting of this bit is not the desirable behavior. WA_1406697149 Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* mesa: Collect all the draw functions in draw.{h,c}.Mathias Fröhlich2018-11-011-0/+1
| | | | | | | | Some of these functions were distributed across different implementation and header files. Put them at a central place. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa/vbo: Move _vbo_draw_indirect -> _mesa_draw_indirectMathias Fröhlich2018-11-011-2/+2
| | | | | Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* configure: allow building with python3Emil Velikov2018-10-311-1/+1
| | | | | | | | | | | | | | | Pretty much all of the scripts are python2+3 compatible. Check and allow using python3, while adjusting the PYTHON2 refs. Note: - python3.4 is used as it's the earliest supported version - python2 chosen prior to python3 v2: use python2 by default Cc: Ilia Mirkin <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* i965: Disable dual source blending when shader doesn't support it on gen8+Danylo Piliaiev2018-10-301-3/+42
| | | | | | | | | | | | | | | | | | | Dual source blending behaviour is undefined when shader doesn't have second color output, dismissing fragment in such situation leads to a hang on gen8+ if depth test in enabled. Since blending cannot be gracefully fixed in such case and the result is undefined - blending is simply disabled. v2 (Kenneth Graunke): - Listen to BRW_NEW_FS_PROG_DATA in 3DSTATE_PS_BLEND - Also whack BLEND_STATE[] to keep the two in sync, since we're not sure exactly which copy of the redundant info the hardware will use. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107088 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Respect GL_TEXTURE_SRGB_DECODE_EXT in GenerateMipmaps()Kenneth Graunke2018-10-301-1/+18
| | | | | | | | | | | Apparently, we're supposed to look at the texture object's built-in sampler object's sRGB decode setting in order to decide whether to decode/downsample/re-encode, or simply downsample as-is. Previously, I had always done the decoding/encoding. Fixes SKQP's Skia_Unit_Tests.SRGBMipMaps test. Reviewed-by: Tapani Pälli <[email protected]>
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