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path: root/src/mesa/drivers
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* i965: Remove end-of-thread SEND alignment code.Matt Turner2015-05-051-12/+3
* i965: Add XRGB8888 format to intel_screen_make_configsBoyan Ding2015-05-051-1/+2
* i965/skl: Align compressed textures to four times the block sizeNeil Roberts2015-05-051-4/+27
* i965: Fix variable indexing of sampler arrays under non-uniform control flow.Francisco Jerez2015-05-043-6/+8
* i965: Fix variable indexing of UBO arrays under non-uniform control flow.Francisco Jerez2015-05-043-10/+11
* i965: Define helper function to copy an arbitrary live component from some re...Francisco Jerez2015-05-044-0/+28
* i965: Perform basic optimizations on the FIND_LIVE_CHANNEL opcode.Francisco Jerez2015-05-046-0/+93
* i965: Introduce the FIND_LIVE_CHANNEL pseudo-opcode.Francisco Jerez2015-05-046-0/+94
* i965: Perform basic optimizations on the BROADCAST opcode.Francisco Jerez2015-05-048-0/+44
* i965: Introduce the BROADCAST pseudo-opcode.Francisco Jerez2015-05-046-0/+98
* i965: Add memory fence opcode.Francisco Jerez2015-05-046-0/+87
* i965: Add typed surface access opcodes.Francisco Jerez2015-05-049-0/+261
* i965: Add untyped surface write opcode.Francisco Jerez2015-05-049-0/+81
* i965: Reorder sources of the untyped atomic opcode.Francisco Jerez2015-05-044-6/+6
* i965: Pass the number of components as a source of the untyped surface read o...Francisco Jerez2015-05-044-6/+10
* i965/vec4: Add support for untyped surface message sends from GRF.Francisco Jerez2015-05-043-16/+14
* i965: Don't request untyped atomic writeback message if the destination is null.Francisco Jerez2015-05-042-2/+3
* i965: Simplify generator code for untyped surface messages.Francisco Jerez2015-05-044-87/+18
* i965: Fix the untyped surface opcodes to deal with indirect surface access.Francisco Jerez2015-05-044-82/+99
* i965: Upload atomic buffer state for compute shadersJordan Justen2015-05-024-1/+29
* i965/cs: Emit MEDIA_STATE_FLUSH after WALKERJordan Justen2015-05-022-0/+6
* i965/cs: Implement brw_emit_gpgpu_walkerJordan Justen2015-05-022-1/+51
* i965/state: Emit pipeline select when changing pipelinesJordan Justen2015-05-024-6/+36
* i965: Implement DispatchCompute() back-endPaul Berry2015-05-024-0/+127
* i965/cs: Emit state base addressJordan Justen2015-05-022-1/+3
* i965/fs: Add CS shader time supportJordan Justen2015-05-024-2/+33
* i965/cs: Upload brw_cs_stateJordan Justen2015-05-024-0/+109
* i965/cs: Support CS program precompileJordan Justen2015-05-024-0/+41
* i965: Add brw_setup_tex_for_precompile. Use in VS, GS & FS.Jordan Justen2015-05-023-24/+24
* i965/cs: Emit compute shader code and upload programsJordan Justen2015-05-023-0/+212
* i965/cs: Set invocation counts based on max_cs_threadsJordan Justen2015-05-021-0/+24
* i965/cs: Add max_cs_threadsJordan Justen2015-05-024-1/+14
* i965: Remove comment about chv device numbers being preliminaryJordan Justen2015-05-021-3/+0
* i965/fs: Support compute programs in fs_visitorJordan Justen2015-05-024-3/+93
* i965/cache: Add support for CS in program state cacheJordan Justen2015-05-024-0/+54
* i965/cs: Add brw_cs_prog_data, brw_cs_prog_key and brw_context::cs.Paul Berry2015-05-022-0/+62
* i965/cs: Add generator support for CS_OPCODE_CS_TERMINATEJordan Justen2015-05-022-0/+36
* i965/cs: Mark g0 as used by CS_OPCODE_CS_TERMINATEJordan Justen2015-05-021-0/+4
* i965/fs: Add emit_cs_terminate to emit CS_OPCODE_CS_TERMINATEJordan Justen2015-05-022-0/+23
* i965/cs: Add CS_OPCODE_CS_TERMINATEJordan Justen2015-05-022-0/+7
* i965/cs: Add BRW_NEW_CS_PROG_DATA and BRW_CACHE_CS_PROGJordan Justen2015-05-023-0/+6
* i965: Add an INTEL_DEBUG=cs option.Paul Berry2015-05-022-2/+4
* i965/cs: Add BRW_NEW_COMPUTE_PROGRAM state flag.Paul Berry2015-05-022-0/+9
* i965/fs: Strip trailing constant zeroes in sample messagesNeil Roberts2015-05-012-0/+50
* i965/skl: Force the exec size to 8 when initing header for SIMD4x2Neil Roberts2015-05-012-0/+2
* i965: Unhardcode a few more stage names and abbreviations.Kenneth Graunke2015-04-302-11/+5
* i965/blorp: Prepare drawing rectangle for flipped coordinatesTopi Pohjolainen2015-04-301-2/+2
* i965/blorp: Add support for layered renderingTopi Pohjolainen2015-04-304-5/+9
* i965/blorp: Allow blend state to be set for multiple render targetsTopi Pohjolainen2015-04-303-19/+18
* i965/blorp: Prepare for attributes other than render positionTopi Pohjolainen2015-04-304-7/+12
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