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* i965: Drop push-mode reladdr constant loading and always use constant_map.Eric Anholt2010-12-084-93/+96
| | | | | | | | This eases the gen6 implementation, which can only handle up to 32 registers of constants, while likely not penalizing real apps using reladdr since all of those I've seen also end up hitting the pull constant buffer. On gen6, the constant map means that simple NV VPs fit under the 32-reg limit and now succeed. Fixes around 10 testcases.
* radeon: bump mip tree levels to 15Alex Deucher2010-12-091-1/+1
| | | | I forgot to bump this when I bumped the tex levels.
* i965: Drop KIL_NV from the ff/ARB_fp path since it was only used for GLSL.Eric Anholt2010-12-083-21/+0
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* i965: Use the new pixel mask location for gen6 ARB_fp KIL instructions.Eric Anholt2010-12-081-2/+8
| | | | | | Fixes: fp-kil fp-generic/kil-swizzle.
* i965: Set the render target index in gen6 fixed-function/ARB_fp path.Eric Anholt2010-12-081-0/+7
| | | | | | Fixes: fbo-drawbuffers2-blend fbo-drawbuffers2-colormask
* i965: Set up the per-render-target blend state on gen6.Eric Anholt2010-12-081-46/+49
| | | | This will let us get EXT_draw_buffers2 blending and colormasking working.
* i965: Set up the color masking for the first drawbuffer on gen6.Eric Anholt2010-12-081-0/+9
| | | | Fixes glean/maskedClear
* r300/compiler: remove at least unused immediates if externals cannot be removedMarek Olšák2010-12-083-8/+6
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* r300/compiler: make lowering passes possibly use up to two less tempsMarek Olšák2010-12-081-63/+86
| | | | | | | | | CMP may now use two less temps, other non-native instructions may end up using one less temp, except for SIN/COS/SCS, which I am leaving unchanged for now. This may reduce register pressure inside loops, because the register allocator doesn't do a very good job there.
* r300/compiler: handle DPH and XPD in rc_compute_sources_for_writemaskMarek Olšák2010-12-081-0/+5
| | | | This bug can only be triggered if you put deadcode before native rewrite.
* r300/compiler: do not print pair/tex/presub program stats for vertex shadersMarek Olšák2010-12-081-16/+30
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* r300/compiler: cleanup rc_run_compilerMarek Olšák2010-12-084-15/+36
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* r300/compiler: add a function to query program stats (alu, tex, temps..)Marek Olšák2010-12-082-15/+39
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* r300/compiler: don't terminate regalloc if we surpass max temps limitMarek Olšák2010-12-081-11/+6
| | | | The same check is already in a later pass (translate_vertex_program).
* i965: Don't try to store gen6 (float) blend constant color in bytes.Eric Anholt2010-12-071-1/+1
| | | | Fixes glean/blendFunc
* i965: Fix flipped value of the not-embedded-in-if on gen6.Eric Anholt2010-12-071-1/+1
| | | | | | Fixes: glean/glsl1-! (not) operator (1, fail) glean/glsl1-! (not) operator (1, pass)
* i965: Work around gen6 ignoring source modifiers on math instructions.Eric Anholt2010-12-073-3/+26
| | | | | | | | | | | | | | | With the change of extended math from having the arguments moved into mrfs and handed off through message passing to being directly hooked up to the EU, it looks like the piece for doing source modifiers (negate and abs) was left out. Fixes: fog-modes glean/fp1-ARB_fog_exp test glean/fp1-ARB_fog_exp2 test glean/fp1-Computed fog exp test glean/fp1-Computed fog exp2 test ext_fog_coord-modes
* i965: Add disabled debug code for dumping out the WM constant payload.Eric Anholt2010-12-071-0/+15
| | | | This can significantly ease thinking about the asm.
* i965: Correctly emit constants for aggregate types (array, matrix, struct)Ian Romanick2010-12-071-19/+61
| | | | | | | Previously the code only handled scalars and vectors. This new code is modeled somewhat after similar code in ir_to_mesa. Reviewed-by: Eric Anholt <[email protected]>
* i965: Always hand the absolute value to RSQ.Eric Anholt2010-12-072-1/+6
| | | | | | | | | | gen6 builtin RSQ apparently clamps negative values to 0 instead of returning the RSQ of the absolute value like ARB_fragment_program desires and pre-gen6 apparently does. Fixes: glean/fp1-RSQ test 2 (reciprocal square root of negative value) glean/vp1-RSQ test 2 (reciprocal square root of negative value)
* i965: Handle saturates on gen6 math instructions.Eric Anholt2010-12-071-0/+2
| | | | | | We get saturate as an argument to brw_math() instead of as compile state, since that's how the pre-gen6 send instructions work. Fixes fp-ex2-sat.
* i965: Fix comment about gen6_wm_constants.Eric Anholt2010-12-071-1/+1
| | | | This is the push constant buffer, not the pull constants.
* i965: upload WM state for _NEW_POLYGON on sandybridgeZhenyu Wang2010-12-071-1/+1
| | | | Be sure polygon stipple mode is updated. This fixes 'gamma' demo.
* r200: Silence uninitialized variable warning.Vinson Lee2010-12-071-0/+1
| | | | | | Fixes this GCC warning. r200_maos_arrays.c: In function 'r200EmitArrays': r200_maos_arrays.c:113: warning: 'emitsize' may be used uninitialized in this function
* i965: set minimum/maximum Point Width on SandybridgeXiang, Haihao2010-12-071-1/+3
| | | | It is used for point width on vertex. This fixes mesa demo spriteblast and pointblast.
* i965: Remove INTEL_DEBUG=glsl_force now that there's no brw_wm_glsl.cEric Anholt2010-12-062-7/+0
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* i965: Nuke brw_wm_glsl.c.Eric Anholt2010-12-068-1057/+10
| | | | | | | | | | It was only used for gen6 fragment programs (not GLSL shaders) at this point, and it was clearly unsuited to the task -- missing opcodes, corrupted texturing, and assertion failures hit various applications of all sorts. It was easier to patch up the non-glsl for remaining gen6 changes than to make brw_wm_glsl.c complete. Bug #30530
* i965: Add support for the instruction compression bits on gen6.Eric Anholt2010-12-064-47/+91
| | | | | | Since the 8-wide first-quarter and 16-wide first-half have the same bit encoding, we now need to track "do you want instruction compression" in the compile state.
* i965: Align gen6 push constant size to dispatch width.Eric Anholt2010-12-061-1/+2
| | | | | | | The FS backend is fine with register level granularity. But for the brw_wm_emit.c backend, it expects pairs of regs to be used for the constants, because the whole world is pairs of regs. If an odd number got used, we went looking for interpolation in the wrong place.
* i965: Make the sampler's implied move on gen6 be a raw move.Eric Anholt2010-12-061-1/+1
| | | | We were accidentally doing a float-to-uint conversion.
* i965: Fix up gen6 samplers for their usage by brw_wm_emit.cEric Anholt2010-12-061-7/+9
| | | | | We were trying to do the implied move even when we'd already manually moved the real header in place.
* i965: Fix gen6 interpolation setup for 16-wide.Eric Anholt2010-12-061-15/+26
| | | | | | In the SF and brw_fs.cpp fixes to set up interpolation sanely on gen6, the setup for 16-wide interpolation was left behind. This brings relative sanity to that path too.
* i965: Don't smash a group of coordinates doing gen6 16-wide sampler headers.Eric Anholt2010-12-061-0/+1
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* i965: Fix up 16-wide gen6 FB writes after various refactoring.Eric Anholt2010-12-061-9/+8
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* i965: Provide delta_xy reg to gen6 non-GLSL path PINTERP.Eric Anholt2010-12-061-8/+6
| | | | Fixes many assertion failures in that path.
* i965: Move payload reg setup to compile, not lookup time.Eric Anholt2010-12-069-110/+118
| | | | | | | | Payload reg setup on gen6 depends more on the dispatch width as well as the uses_depth, computes_depth, and other flags. That's something we want to decide at compile time, not at cache lookup. As a bonus, the fragment shader program cache lookup should be cheaper now that there's less to compute for the hash key.
* i965: Fix GS state uploading on SandybridgeZhenyu Wang2010-12-062-5/+14
| | | | | | | | Need to check the required primitive type for GS on Sandybridge, and when GS is disabled, the new state has to be issued too, instead of only updating URB state with no GS entry, that caused hang on Sandybridge. This fixes hang issue during conformance suite testing.
* i965: fix for flat shading on SandybridgeXiang, Haihao2010-12-061-2/+9
| | | | | use constant interpolation instead of linear interpolation for attributes COL0,COL1 if GL_FLAT is used. This fixes mesa demo bounce.
* i965: Fix compile warning about missing opcodes.Eric Anholt2010-12-041-0/+5
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* i965: Update gen6 SF state on fragment program change too.Eric Anholt2010-12-041-1/+3
| | | | | SF state depends on what inputs there are to the fragment program, not just the outputs of the VS.
* i965: Update gen6 WM state on compiled program change, not just FP change.Eric Anholt2010-12-041-1/+3
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* intel: Add an env var override to execute for a different GPU revision.Eric Anholt2010-12-044-9/+15
| | | | | | | Sometimes I'm on the train and want to just read what's generated under INTEL_DEBUG=vs,wm for some code on another generation. Or, for the next gen enablement we'll want to dump aub files before we have the actual hardware. This will let us do that.
* r600c: bump texture limits to hw limitsAlex Deucher2010-12-021-2/+7
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* WIN32_THREADS -> WIN32José Fonseca2010-12-021-2/+3
| | | | | | | | | Fixes nasty bug where some parts of the code didn't define WIN32_THREADS and were using the integer mutex implementation, causing even confusion to the debuggers. And there is little interest of other thread implemenation on Win32 besides Win32 threads.
* r300/compiler: disable the swizzle lowering pass in vertex shadersMarek Olšák2010-12-021-1/+0
| | | | It was a no-op because all swizzles are native there.
* i965: add support for polygon mode on Sandybridge.Xiang, Haihao2010-12-021-0/+42
| | | | This fixes some mesa demos such as fslight/engine in wireframe mode.
* i965: Add support for loops in the VS.Eric Anholt2010-12-011-25/+33
| | | | This follows the changes done for the FS alongside the EU emit code.
* i965: Enable IF statements in the VS.Eric Anholt2010-12-011-3/+0
| | | | | While the actual IF instructions were fixed by Zhenyu, we were still flattening them to conditional moves.
* i965: Add support for gen6 CONTINUE instruction emit.Eric Anholt2010-12-013-4/+28
| | | | At this point, piglit tests for fragment shader loops are working.
* i965: Add support for gen6 BREAK ISA emit.Eric Anholt2010-12-014-10/+112
| | | | | There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels.
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