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* i965: Clean up some mess with the batch cache.Eric Anholt2009-09-243-18/+5
| | | | | Its flagging of extra state that's already flagged by the vtbl new_batch when appropriate was confusing my tracking down of the OA clear bug.
* i965: Emit zero initialization for NV VP temporaries as required.Eric Anholt2009-09-241-0/+1
| | | | | | | This is similar to what r300 does inside the driver, but I've added it as a generic option since it seems most hardware will want it. Fixes piglit nv-init-zero-reg.vpfp and nv-init-zero-addr.vpfp.
* i965: Remove assert about NV_vp now that it somewhat works.Eric Anholt2009-09-241-2/+0
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* i965: Load NV program matrices when required.Eric Anholt2009-09-241-0/+3
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* intel: use default array/element buffers in intel_generate_mipmap()Brian Paul2009-09-241-0/+21
| | | | | | | If there happened to be a bound VBO when intel_generate_mipmap() was called we blew up because of a bad vertex array pointer. Fixes regnumonline, bug 23859.
* radeon: Fix scissors for r600 KMS.Pauli Nieminen2009-09-242-6/+7
| | | | | | | Radeon generic scissors code had problem that some of code was using exclusive and some inclusive bottom right corner. Only r600 driver is using exclusive coordinate so changed generic code to pass inclusive coordinate and r600 driver changes BR coordinate to be exclusive.
* r600: add support for CUBE textures, also TXPAndre Maasikas2009-09-242-47/+263
| | | | seems to work here ...
* r600: fix typo in the last commitAlex Deucher2009-09-241-5/+5
| | | | 128 gprs, 256 reg-based consts
* r600: various cleanupsAlex Deucher2009-09-243-45/+24
| | | | | | | | | | | | - max texture size is 8k, but mesa doesn't support that at the moment. - attempt to set shader limits to what the hw actually supports - clean up some old r300 cruft - no need to explicitly disable irqs. This is fixed in the drm now. Signed-off-by: Alex Deucher <[email protected]>
* r600: fix some issues with LIT instructionAndre Maasikas2009-09-241-33/+36
| | | | | | | | - MUL_LIT is ALU.Trans instruction - some Trans instructions can take 3 arguments - don't clobber dst.x, use dst.z as temp, it'll get written correct value in last insn - respect source swizzles
* r600: fix point sizesAlex Deucher2009-09-241-4/+4
| | | | registers takes radius
* r600: fix polygon offsetAlex Deucher2009-09-241-3/+8
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* radeon: don't build non-r600 span code on r600Alex Deucher2009-09-241-1/+5
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* r600: minor span cleanupsAlex Deucher2009-09-241-4/+3
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* r600: support position_invariant programsAndre Maasikas2009-09-241-12/+18
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* r600: add span support for 1D tilesAlex Deucher2009-09-243-1/+223
| | | | | | | | | | | 1D tile span support for depth/stencil/color/textures Z and stencil buffers are always tiled, so this fixes sw access to Z and stencil buffers. color and textures are currently linear, but this adds span support when we implement 1D tiling. This fixes the text in progs/demos/engine and progs/tests/z*
* r600: fix warningAlex Deucher2009-09-241-0/+1
| | | | Noticed by rnoland on IRC.
* r600: fix texcoords from constantsAndre Maasikas2009-09-241-40/+52
| | | | with some minor updates from Richard.
* r600: enable caching of vertex programsAndre Maasikas2009-09-246-62/+110
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* r600: check if textures are actually enabled before submissionAlex Deucher2009-09-242-56/+64
| | | | noticed by taiu on IRC.
* r600: fix ftp for dri1Alex Deucher2009-09-241-3/+4
| | | | We use t->bo for dri1 since r600 uses CS for dri1.
* r600: don't setup hardware state if TFPDave Airlie2009-09-241-0/+4
| | | | | | | if we have a BO here it means TFP and we should have set it up already. tested by b0le on #radeon
* r600: fix dri2 clippingAlex Deucher2009-09-241-2/+2
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* r300: fallback to software rendering if we are out of free texcoordsMaciej Cencora2009-09-231-2/+16
| | | | Fixes #22741
* mesa: don't re-use the meta glDrawPixels VBO; create a new one each timeBrian Paul2009-09-221-30/+22
| | | | This should help to work around bugs 24083 and 23670.
* r300: Fix crash reported in bug #24066Nicolai Hähnle2009-09-221-0/+15
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* radeon: update buffer map/unmap code for changes introduced in ↵Maciej Cencora2009-09-211-2/+9
| | | | 92033a9516942d7272ce4bf36ecd422009bbaf60 and 822c7964819ca1fcc270880d4ca8b3de8a4276d0
* r300: fix a typoMaciej Cencora2009-09-211-1/+1
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* r300: Zero-initialize register for NV_vertex_programNicolai Hähnle2009-09-212-0/+32
| | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* r300: Fix handling of NV_vertex_program parametersNicolai Hähnle2009-09-211-6/+29
| | | | | | | The handling is a bit inefficient, unfortunately, but I don't want to make any intrusive changes for Mesa 7.6. Signed-off-by: Nicolai Hähnle <[email protected]>
* Merge branch 'mesa_7_5_branch' into mesa_7_6_branchMichel Dänzer2009-09-211-1/+2
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| * intel: Fix crash in intel_flush().Michel Dänzer2009-09-211-1/+2
| | | | | | | | | | | | Since commit 2921a2555d0a76fa649b23c31e3264bbc78b2ff5 ('intel: Deassociated drawables from private context struct in intelUnbindContext'), intel->driDrawable may be NULL in intel_flush().
* | radeon: Fix legacy bo not to reuse dma buffers before refcount is 1.Pauli Nieminen2009-09-201-2/+7
| | | | | | | | | | This should help detecting possible memory leaks with dma buffers and prevent possible visual corruption if data would be overwriten too early.
* | r300/compiler: Fix trig instructions in R300 fpNicolai Hähnle2009-09-201-9/+9
| | | | | | | | Signed-off-by: Nicolai Hähnle <[email protected]>
* | radeon: Fix typo in variable name.Pauli Nieminen2009-09-201-1/+1
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* | radeon: Improve WARN_ONCE macro to appear as single statement.Pauli Nieminen2009-09-201-5/+6
| | | | | | | | | | | | Do-while makes macro safe to be used with if and for constructions. Also remove __LINE__ macro from variable name because scope is local to macro anyway.
* | radeon: Fix "verts" debugging enableNicolai Hähnle2009-09-201-1/+1
| | | | | | | | | | | | Copy'n'paste apparently prevented the RADEON_VERTS flag from being enabled. Signed-off-by: Nicolai Hähnle <[email protected]>
* | r300/compiler: Fix R300 fragment program regression introduced by 0723cd1...Nicolai Hähnle2009-09-201-1/+1
| | | | | | | | | | | | | | | | | | We obviously need to move the code addr register backwards because their may be overlap. This bug affected in particular the Compiz water plugin. Signed-off-by: Nicolai Hähnle <[email protected]>
* | [i965] add a missing header fileZou Nan hai2009-09-181-0/+1
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* | [i965] use intel_batchbuffer_flush to flush the clearZou Nan hai2009-09-181-1/+2
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* | mesa: fix clip plane, fog issuesBrian Paul2009-09-161-4/+0
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* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick2009-09-161-0/+8
|\| | | | | | | | | Conflicts: src/mesa/main/dlist.c
| * intel: Deassociated drawables from private context struct in intelUnbindContextIan Romanick2009-09-161-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | The generic DRI infrastructure makes sure that __DRIcontextRec::driDrawablePriv and __DRIcontextRec::driReadablePriv are set to NULL after unbinding a context. However, the intel_context structure keeps cached copies of these pointers. If these cached pointers are not NULLed and the drawable is actually destroyed after unbinding the context (typically by way of glXDestroyWindow), freed memory will be dereferenced in intelDestroyContext. This should fix bug #23418.
* | i965: do a flush in clear, fix openarena render issue,Zou Nan hai2009-09-161-0/+1
| | | | | | | | fd.o bug# 23857
* | radeon: Remove structure allocation from iterator variable.Pauli Nieminen2009-09-111-1/+1
| | | | | | | | | | dma_bo varaible is only used for iterating so allocating memory for it only causes memory leaks.
* | intel: disable intel_stencil_drawpixels() for nowBrian Paul2009-09-101-0/+16
| | | | | | | | It doesn't work reliably even when all the prerequisite checks are made.
* | Fix merge failIan Romanick2009-09-101-13/+0
| | | | | | | | | | | | | | | | | | One of the conflicst from this merge was missed: commit 0c309bb494b6ee1c403442d1207743f749f95b6e Merge: c6c44bf d27d659 Author: Brian Paul <[email protected]> Date: Wed Sep 9 08:33:39 2009 -0600
* | mesa: need to set all stencil bits to 0 before setting the 1 bitsBrian Paul2009-09-101-0/+9
| | | | | | | | Plus, check for pixel transfer stencil index/offset.
* | Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick2009-09-102-1/+6
|\| | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_context.c
| * intel: add B43 chipset supportZhenyu Wang2009-09-102-1/+6
| | | | | | | | | | | | | | | | | | Signed-off-by: Zhenyu Wang <[email protected]> Signed-off-by: Ian Romanick <[email protected]> Hopefully this will be one of the last cherry-picks. (cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
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