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path: root/src/mesa/drivers
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* i965: Prevent fast clears for MSRTs on SKLNeil Roberts2015-11-181-0/+7
* i965: Fix PIPE_CONTOL typo.Kenneth Graunke2015-11-171-1/+1
* i965: Add assertion for src_stencil payload sizeBen Widawsky2015-11-171-0/+6
* i965: Implement ARB_pipeline_statistics_query tessellation counters.Kenneth Graunke2015-11-171-8/+8
* i965: Add INTEL_DEBUG=shader_time support for tessellation shaders.Kenneth Graunke2015-11-172-0/+14
* i965: Add INTEL_DEBUG=tcs,tes and hs,ds flags for tessellation shaders.Kenneth Graunke2015-11-172-2/+8
* i965: Add more MAX_*_URB_ENTRY_SIZE_BYTES #defines.Kenneth Graunke2015-11-171-0/+6
* i965: Add missing stdio.h include to brw_compiler.h.Kenneth Graunke2015-11-171-0/+1
* i965: Return the correct value type from brw_compile_gs()Eduardo Lima Mitev2015-11-171-1/+1
* i965: Set MaxCombinedUniformBlocks properly.Kenneth Graunke2015-11-161-0/+1
* i965: Clean up context constant initialization code.Kenneth Graunke2015-11-161-80/+54
* i965: Convert scalar_* flags to a scalar_stage array.Kenneth Graunke2015-11-1610-39/+27
* r200: fix bgrx8/xrgb8 blitsRoland Scheidegger2015-11-171-0/+4
* radeon: fix bgrx8/xrgb8 blitsRoland Scheidegger2015-11-171-0/+2
* meta/generate_mipmap: Only modify the draw framebuffer binding in fallback_re...Ian Romanick2015-11-161-4/+4
* i965: Introduce a MOV_INDIRECT opcode.Kenneth Graunke2015-11-146-0/+80
* i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.Kenneth Graunke2015-11-134-5/+10
* i965: Print input/output VUE maps on INTEL_DEBUG=vs, gs.Kenneth Graunke2015-11-134-1/+40
* i965: Make convert_attr_sources_to_hw_regs handle stride == 0.Kenneth Graunke2015-11-131-1/+2
* i965: Silence unused parameter warnings in get_buffer_rectIan Romanick2015-11-131-4/+3
* meta/generate_mipmap: Don't leak the sampler objectIan Romanick2015-11-131-0/+2
* i965: Remove unneeded #includes.Matt Turner2015-11-131-4/+0
* i965: Silence warning.Matt Turner2015-11-131-2/+2
* i965: Don't write beyond allocated memory.Juha-Pekka Heikkila2015-11-131-1/+1
* i965: Use BRW_MRF_COMPR4 macro in more places.Matt Turner2015-11-134-6/+6
* i965: Combine register file field.Matt Turner2015-11-137-34/+27
* i965: Replace HW_REG with ARF/FIXED_GRF.Matt Turner2015-11-1313-211/+157
* i965/fs: Set stride correctly for immediates in fs_reg(brw_reg).Matt Turner2015-11-131-0/+6
* i965/fs: Handle type-V immediates in brw_reg_from_fs_reg().Matt Turner2015-11-131-0/+3
* i965: Rename GRF to VGRF.Matt Turner2015-11-1330-194/+194
* i965: Move BAD_FILE from the beginning of enum register_file.Matt Turner2015-11-131-1/+1
* i965: Initialize registers.Matt Turner2015-11-133-2/+18
* i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-1325-290/+276
* i965: Unwrap some lines.Matt Turner2015-11-134-12/+4
* i965/vec4: Remove swizzle/writemask fields from src/dst_reg.Matt Turner2015-11-132-8/+1
* i965: Remove fixed_hw_reg field from backend_reg.Matt Turner2015-11-1311-162/+139
* i965: Use immediate storage in inherited brw_reg.Matt Turner2015-11-1310-95/+96
* i965: Add and use enum brw_reg_file.Matt Turner2015-11-134-19/+23
* i965: Reorganize brw_reg fields.Matt Turner2015-11-131-8/+8
* i965: Make 'dw1' and 'bits' unnamed structures in brw_reg.Matt Turner2015-11-1314-178/+185
* i965: Delete type field from backend_reg.Matt Turner2015-11-131-1/+0
* i965: Delete abs/negate fields from backend_reg.Matt Turner2015-11-133-5/+2
* i965: Make backend_reg inherit from brw_reg.Matt Turner2015-11-131-3/+3
* i965/fs: Replace nested ternary with if ladder.Matt Turner2015-11-131-6/+7
* mesa: In helpers, only check driver capability for metaNanley Chery2015-11-122-0/+12
* i965: Check instructions appear only on supported hardware.Matt Turner2015-11-121-0/+254
* i965: Add initial assembly validation pass.Matt Turner2015-11-125-0/+174
* i965: Add annotation_insert_error() and support for printing errors.Matt Turner2015-11-122-7/+71
* i965: Combine assembly annotations if possible.Matt Turner2015-11-121-5/+18
* i965: Set annotation_info's mem_ctx.Matt Turner2015-11-123-2/+5
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