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* android: add gallium dirs to more places in the treeEmil Velikov2015-04-221-0/+2
* android: dri/common: conditionally include drm_cflags/set __NOT_HAVE_DRM_HEmil Velikov2015-04-221-0/+14
* android: add $(mesa_top)/src include to the whole of mesaEmil Velikov2015-04-221-1/+0
* android: use LOCAL_SHARED_LIBRARIES over TARGET_OUT_HEADERSEmil Velikov2015-04-221-1/+0
* drirc: Add "Second Life" quirk (allow_glsl_extension_directive_midshader).Kenneth Graunke2015-04-211-0/+4
* i965/fs: Combine pixel center calculation into one inst.Matt Turner2015-04-213-20/+63
* i965/fs: Calculate delta_x and delta_y together.Matt Turner2015-04-217-74/+79
* i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.Matt Turner2015-04-215-51/+8
* i965/fs: Manually set source regioning on PLN instructions.Matt Turner2015-04-211-1/+13
* i965/fs: Add LINTERP's src0 to fs_inst::regs_read().Matt Turner2015-04-211-11/+2
* i965/fs: Set compression only if writing two registers.Matt Turner2015-04-211-1/+4
* i965/fs: Allow an execution size of 32.Matt Turner2015-04-212-1/+2
* i965: Make type_sz() return unsigned.Matt Turner2015-04-211-1/+1
* i965: Replace guess_execution_size with something simpler.Matt Turner2015-04-214-27/+35
* i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.Matt Turner2015-04-212-3/+3
* radeon: replace __FUNCTION__ with __func__Marius Predut2015-04-2132-116/+116
* i965/skl: Fix the qpitch valueNeil Roberts2015-04-202-13/+59
* i965/skl: Don't use ALL_SLICES_AT_EACH_LODNeil Roberts2015-04-201-10/+20
* i965: Issue perf_debug messages for unsynchronized maps on !LLC systems.Kenneth Graunke2015-04-171-5/+11
* i965: Make shader_time store names/ids instead of referencing shaders.Kenneth Graunke2015-04-172-37/+19
* i965: Delete some unnecessary code in brw_report_shader_time().Kenneth Graunke2015-04-171-6/+1
* i965: Make shader_time use 0 instead of -1 for "no meaningful ID".Kenneth Graunke2015-04-171-8/+6
* adjust a couple of ifdefs to handle NetBSD correctlyTobias Nygren2015-04-171-1/+1
* i965: Render R16G16B16X16 as R16G16B16A16Anuj Phogat2015-04-171-0/+6
* i965: Update the comment about platforms supporting blorpAnuj Phogat2015-04-171-2/+2
* i965/fs: Change SEL and MOV types as needed to propagate source modifiersJason Ekstrand2015-04-171-4/+30
* i965/fs: Use the source type when looking for UD negations in copy propJason Ekstrand2015-04-171-1/+1
* i965: Rewrite ir_tex to ir_txl with lod 0 for vertex shadersKristian Høgsberg2015-04-161-0/+9
* i965/skl: Add the header for constant loads outside of the generatorNeil Roberts2015-04-166-35/+63
* i965/vec4: Add a helper function to emit VS_OPCODE_PULL_CONSTANT_LOADNeil Roberts2015-04-163-77/+75
* i965/fs: Combine tex/fb_write operations (opt)Ben Widawsky2015-04-143-0/+103
* i965/fs: Only emit FS_OPCODE_PLACEHOLDER_HALT if there are discardsBen Widawsky2015-04-141-1/+4
* i965/fs: Create a has_side_effects for fs_instBen Widawsky2015-04-142-0/+7
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-1424-72/+72
* i915: replace __FUNCTION__ with __func__Marius Predut2015-04-1424-107/+107
* swrast: replace __FUNCTION__ with __func__Marius Predut2015-04-142-3/+3
* i965/fs: Correct mistake in determining whether a MUL is negated.Matt Turner2015-04-141-1/+1
* i965/skl: Use an exec size of 8 to initialise the message headerNeil Roberts2015-04-142-2/+2
* i965/fs: Always invert predicate of SEL with swapped argumentsIan Romanick2015-04-141-5/+5
* i965: Implement proper workaround for Gen4 GPU CONSTANT_BUFFER hangs.Kenneth Graunke2015-04-141-13/+26
* i965: Fix INTEL_DEBUG=shader_time for SIMD8 VS.Kenneth Graunke2015-04-141-0/+3
* i965: Flush batchbuffer containing the query on glQueryCounter.Mathias Froehlich2015-04-131-0/+2
* i965: Don't bother freeing NULL.Matt Turner2015-04-131-4/+2
* i965: Lift some restrictions on dma_buf EGLImagesChad Versace2015-04-133-22/+7
* i965: Disable aux buffers for EGLImage-backed miptreesChad Versace2015-04-132-5/+19
* i965: Change intel_miptree_create_for_bo() signatureChad Versace2015-04-136-11/+21
* i965: Add field intel_mipmap_tree::disable_aux_buffersChad Versace2015-04-132-2/+29
* i965: Refactor brw_is_hiz_depth_format()Chad Versace2015-04-135-25/+30
* i965: Declare intel_miptree_create_layout() as staticChad Versace2015-04-132-14/+1
* i965: Declare intel_miptree_alloc_mcs() as staticChad Versace2015-04-132-6/+6
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