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* radeon&r200: Add support for ARB_sampler_objectsPauli Nieminen2012-08-0110-39/+67
| | | | | | | | Preparation for the mandatory support of ARB_sampler_objects. I have tested this patch with rv280 only. Signed-off-by: Pauli Nieminen <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon: Fix printf format not to warn in 64bitPauli Nieminen2012-08-011-2/+2
| | | | | | | | | When I build tested radeon changes I noticed two warnings about format size missmatch in 64bit. I decided to clean them to make relevant compiler warnings easier to spot. Signed-off-by: Pauli Nieminen <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nouveau: Add support for ARB_sampler_objectsPauli Nieminen2012-08-014-31/+46
| | | | | | | | | | | | ARB_sampler_objects is very simple software only extension to support. I want to make it a mandatory extension for Mesa drivers to allow the meta module to use it. This patch add support for the extension to nouveau. It is completely untested search and replace patch, except for flagging the texture state as needing to be recomputed when a sampler object is present. Signed-off-by: Pauli Nieminen <[email protected]>
* mesa: Move DepthMode to texture objectPauli Nieminen2012-08-014-4/+4
| | | | | | | | | | | | | | | | | | | | | | | GL_DEPTH_TEXTURE_MODE isn't meant to be part of sampler state based on compatibility profile specifications. OpenGL specification 4.1 compatibility 20100725 3.9.2: "... The values accepted in the pname parameter are TEXTURE_WRAP_S, TEXTURE_WRAP_T, TEXTURE_WRAP_R, TEXTURE_MIN_- FILTER, TEXTURE_MAG_FILTER, TEXTURE_BORDER_COLOR, TEXTURE_MIN_- LOD, TEXTURE_MAX_LOD, TEXTURE_LOD_BIAS, TEXTURE_COMPARE_MODE, and TEXTURE_COMPARE_FUNC. Texture state listed in table 6.25 but not listed here and in the sampler state in table 6.26 is not part of the sampler state, and remains in the texture object." The list of states is in Table 6.24 "Textures (state per texture object)" instead of 6.25 mentioned in the specification text. Same can be found from 3.3 compatibility specification. Signed-off-by: Pauli Nieminen <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/msaa: Allow GL_SAMPLES to be set to 1 prior to Gen6.Paul Berry2012-08-011-1/+9
| | | | | | | | | | | | This patch allows GL_SAMPLES to be set to either 0 or 1 on i965 platforms that don't support MSAA (those prior to Gen6). Setting GL_SAMPLES=1 has the same effect as setting it to 0 on these platforms (because MSAA is unsupported), but is distinguishable via the GL API. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50165 Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/msaa: Treat GL_SAMPLES=1 as equivalent to GL_SAMPLES=0.Paul Berry2012-08-0111-22/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EXT_framebuffer_multisample is a required subpart of ARB_framebuffer_object, which means that we must support it even on platforms that don't support MSAA. Fortunately EXT_framebuffer_multisample allows for this by allowing GL_MAX_SAMPLES to be set to 1. This leads to a tricky quirk in the GL spec: since GlRenderbufferStorageMultisamples() accepts any value for its "samples" parameter up to and including GL_MAX_SAMPLES, that means that on platforms that don't support MSAA, GL_SAMPLES is allowed to be set to either 0 or 1. On platforms that do support MSAA, GL_SAMPLES=1 is not used; 0 means no MSAA, and 2 or higher means MSAA. In other words, GL_SAMPLES needs to be interpreted as follows: =0 no MSAA (possible on all platforms) =1 no MSAA (only possible on platforms where MSAA unsupported) >1 MSAA (only possible on platforms where MSAA supported) This patch modifies all MSAA-related code to choose between multisampling and single-sampling based on the condition (GL_SAMPLES > 1) instead of (GL_SAMPLES > 0) so that GL_SAMPLES=1 will be treated as "no MSAA". Note that since GL_SAMPLES=1 implies GL_SAMPLE_BUFFERS=1, we can no longer use GL_SAMPLE_BUFFERS to distinguish between MSAA and non-MSAA rendering. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* intel: Use consistent pattern in intelCreateBufferChad Versace2012-08-011-4/+2
| | | | | | | The 16-bit depth case did not follow the function's prevalent pattern. Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Decrease nesting level in intelCreateBufferChad Versace2012-08-011-66/+63
| | | | | | | | | | Nearly the whole function body was contained in the 'else' branch. The 'if' branch did one thing: return early with an error. Clean things up by moving all the code out of the 'else' branch. Decreases max nesting level from 4 to 3. Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Remove dead code in intelAllocateBufferChad Versace2012-08-011-85/+7
| | | | | | | | | | | After commit "intel: Convert to using private depth/stencil buffers", we request from DRI2GetBuffersWithFormat only the front left and back left buffers. We no longer request depth and stencil buffers. Assert that in intelAllocateBuffer and remove the related dead code. Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* r200: get rid of dubious aux scissor bitsRoland Scheidegger2012-08-012-24/+15
| | | | | | | | | no point in emitting aux scissor values if we a) never enable them b) never set the actual values plus it is enough to have that aux scissor enable reg (which we never set to enable) in one place not two.
* radeon/r200: get rid of some unneeded cliprect/scissor codeRoland Scheidegger2012-08-014-62/+3
| | | | | Noone was interested in the number of cliprects, and noone cared about the intersect result neither. So just nuke this.
* r200: get rid of old gart memory functions from old dri1Roland Scheidegger2012-08-012-32/+0
| | | | Those functions are SO dead.
* radeon/r200: fix bogus clearsRoland Scheidegger2012-08-012-52/+22
| | | | | | | | | There were several problems with these functions (which are a remnant of dri1 hyperz mostly - should bring it back somehow someday). First, it would always do a swrast clear if the buffer to clear was a fbo. Second, for buffers we wouldn't handle the clear (I guess aux/accum?) we would actually still have tried to clear that later even when we already cleared it with swrast.
* radeon/r200: fix bogus assert/scissor wrt width/height 2048Roland Scheidegger2012-08-012-8/+8
| | | | | | | | | This addresses one issue raised in bug #51658 discovered by Eugene St Leger. The assert is bogus since there's no problem with texture width/height being 2048 (the width/height programmed is width/height minus one). OTOH though the programmed size for scissor rect should be width/height minus one too otherwise bad things may happen (as it is inclusive, and there's not enough bits for more than a value of 2047).
* i965: Add support for GL_SKIP_DECODE_EXT on other SRGB formats.Eric Anholt2012-07-311-8/+3
| | | | | | | | | | | Fixes some failures in getteximage-formats. v2: Remove stray include, and drop extra test for encoding == GL_SRGB -- _mesa_get_srgb_format_linear() returns the same format if it wasn't SRGB. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48120 Reviewed-by: Kenneth Graunke <[email protected]> (v1) NOTE: This is a candidate for the 8.0 branch.
* Move installing osmesa.pc to drivers/osmesaJon TURNEY2012-07-312-2/+15
| | | | | | | | | | | | | | | | Move installing osmesa.pc to drivers/osmesa, where it belongs better This also restores the installation of gl.pc if we are building osmesa at the same time as libGL, which was broken in commit 39785488 when the .pc installation was converted to automake v2: Remove HAVE_OSMESA_DRIVER automake conditional, it's now pointless as we will only be building in the drivers/osmesa directory if the condition it checked was true. Signed-off-by: Jon TURNEY <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: add support for using API_OPENGL_COREJordan Justen2012-07-301-1/+1
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* meta: add support for using API_OPENGL_COREJordan Justen2012-07-301-1/+1
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Support MESA_FORMAT_SIGNED_RGBA_16.Kenneth Graunke2012-07-301-1/+1
| | | | | | | | | | | | | | | | The hardware supports this format with no known quirks, so we may as well enable it. Alpha blending is not supported until Sandybridge, but as far as I can tell, OpenGL doesn't require alpha blending on SNORM formats. Plus, we already expose R8G8B8A8_SNORM which has a similar restriction. Fixes 6 piglit texwrap-2D-*SNORM* cases, gl-3.1/required-sized-texture-formats, and 10 oglconform snorm-textures subcases Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meta: fix glDrawPixels fallback test, stencil drawingBrian Paul2012-07-271-2/+2
| | | | | | | | | | | | | | | | | | Remove the check for pixel transfer ops. If any RGB/depth scale/bias is in effect, it'll be applied in the glTexImage step. If drawing stencil pixels we need to disable pixel transfer so that alpha scale/bias are not applied to the stencil data. These issues were spotted by Roland. Fixes Blender performance issues reported in http://bugs.freedesktop.org/show_bug.cgi?id=47375 NOTE: This is a candidate for the 8.0 branch. Tested-by: Barto <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeon: fix 'sowftware' typoBrian Paul2012-07-271-1/+1
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* i965/gen7: Reduce GT1 WM thread count according to updated BSpec.Eric Anholt2012-07-271-1/+1
| | | | | | Acked-by: Kenneth Graunke <[email protected]> https://bugs.freedesktop.org/show_bug.cgi?id=52382
* i965: Fix typo in shader channel select field name.Kenneth Graunke2012-07-273-20/+20
| | | | | | "chanel" isn't very searchable. I can type, honest! Signed-off-by: Kenneth Graunke <[email protected]>
* i965/msaa: Use MESA_FORMAT_R8 for MCS buffer.Paul Berry2012-07-271-1/+1
| | | | | | | | | | | | No functional change. This patch modifies intel_miptree_alloc_mcs to allocate the 4x MCS buffer using MESA_FORMAT_R8 instead of MESA_FORMAT_A8. In principle it doesn't matter, since we only access the buffer using MCS-specific hardware mechanisms, so all that's important is to use a format with the correct size. However, MESA_FORMAT_A8 has enough unusual behaviours that it seems prudent to avoid it. Acked-by: Kenneth Graunke <[email protected]>
* intel: increase wm thread number to 80 on gen6 GT2Zou Nan hai2012-07-271-5/+1
| | | | | | | | | | | | | It seems reset is not required for setting the max_wm_threads to 80 on gen6 GT2. Increases performance in the Counter-Strike: Source video stress test by 7.18% (n=5). Signed-off-by: Zou Nan hai <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Matt Turner <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965/msaa: use ROUND_DOWN_TO macro.Paul Berry2012-07-261-6/+6
| | | | | | | | No functional change. This patch modifies brw_blorp_blit.cpp to use the ROUND_DOWN_TO macro instead of open-coded bit manipulations, for clarity. Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: fix Base/base typoBrian Paul2012-07-261-1/+1
| | | | Fixes http://bugs.freedesktop.org/show_bug.cgi?id=52563
* radeon: set swrast_renderbuffer::ColorType field when mapping renderbuffersBrian Paul2012-07-261-0/+2
| | | | | | | | Fixes http://bugs.freedesktop.org/show_bug.cgi?id=47375 NOTE: This is a candidate for the 8.0 branch. Tested-by: Barto <[email protected]>
* xlib: add X error handler around XGetImage() callBrian Paul2012-07-261-0/+29
| | | | | | | | | | XGetImage() will generate a BadMatch error if the source window isn't visible. When that happens, create a new XImage. Fixes piglit 'select' test failures with swrast/xlib driver. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Ian Romanick <[email protected]>
* i965: Use sendc for all render target writes on Gen6+.Paul Berry2012-07-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The sendc instruction causes the fragment shader thread to wait for any dependent threads (i.e. threads rendering to overlapping pixels) to complete before sending the message. We need to use sendc on the first render target write in order to guarantee that fragment shader outputs are written to the render target in the correct order. Previously, we only used the "sendc" instruction when writing to binding table index 0. This did the right thing for fragment shaders, because our fragment shader back-ends always issue their first render target write to binding table index 0. However, it did the wrong thing for blorp, which performs its render target writes to binding table index 1. A more robust solution is to use sendc for all render target writes. This should not produce any performance penalty, since after the first sendc, all of the dependent threads will have completed. For more information about sendc, see the Ivy Bridge PRM, Vol4 Part3 p218 (sendc - Conditional Send Message), and p54 (TDR Registers). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/msaa: Remove TODO comments that are no longer relevant.Paul Berry2012-07-262-3/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Make more consistent use of _mesa_is_{user,winsys}_fbo()Paul Berry2012-07-269-12/+19
| | | | | | | | | | A lot of code was still differentiating between between winsys and user fbos by testing the fbo's name against zero. This converts everything in the i915 and 965 drivers over to use _mesa_is_user_fbo() and _mesa_is_winsys_fbo(). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove unused param conversion code.Eric Anholt2012-07-257-80/+3
| | | | | | | | Ever since ctx->NativeIntegers was set, the conversion flag has been PARAM_NO_CONVERT. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* Update mesa/drivers/x11/Makefile.am for xm_image.h removalJon TURNEY2012-07-251-1/+0
| | | | | | | | | | | | | | Commit 6c6803f28de0d4cb6937fcd95a47aa81da31fd78 removed xm_image.[ch], and removed xm_image.c, but not xm_image.h from the Makefile, this was subsequently carried over into Makefile.am Remove xm_image.h from Makfile.am. This allows 'make dist' to succeed, even if it doesn't do anything useful Signed-off-by: Jon TURNEY <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* drivers/osmesa: Link OSMesa using -no-undefined libtool flagJon TURNEY2012-07-251-1/+1
| | | | | | | | | | | | "Use -no-undefined to assure libtool that the library has no unresolved symbols at link time, so that libtool will build a shared library on platforms require that all symbols are resolved when the library is linked." Signed-off-by: Jon TURNEY <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* drivers/X11: Link X11 libGL with -no-undefined libtool flagJon TURNEY2012-07-251-0/+1
| | | | | | | | | | | | "Use -no-undefined to assure libtool that the library has no unresolved symbols at link time, so that libtool will build a shared library on platforms require that all symbols are resolved when the library is linked." Signed-off-by: Jon TURNEY <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/msaa: Switch on 8x MSAA for Gen7.Paul Berry2012-07-242-3/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Adjust MCS buffer allocation for 8x MSAA.Paul Berry2012-07-241-2/+25
| | | | | | | | MCS buffers use 32 bits per pixel in 8x MSAA, and 8 bits per pixel in 4x MSAA. This patch adjusts the format we use to allocate the buffer so that enough memory is set aside for 8x MSAA. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Remove assertion in 3DSTATE_SAMPLE_MASK to allow 8x MSAA.Paul Berry2012-07-241-3/+0
| | | | | | | | The code to emit 3DSTATE_SAMPLE_MASK was already correct for 8x MSAA--this patch just removes an assertion that would have prevented it from being used for 8x MSAA. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Adjust 3DSTATE_MULTISAMPLE packet for 8x MSAA.Paul Berry2012-07-241-6/+64
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Encode and decode IMS format for 8x MSAA correctly.Paul Berry2012-07-241-39/+107
| | | | | | | | This patch updates the blorp functions encode_msaa() and decode_msaa() to properly handle the encoding of IMS MSAA buffers when num_samples=8. Acked-by: Kenneth Graunke <[email protected]>
* i965/blorp: Compute sample number correctly for 8x MSAA.Paul Berry2012-07-241-13/+42
| | | | | | | | | | When operating in persample dispatch mode, the blorp engine would previously assume that subspan N always represented sample N (this is correct assuming 4x MSAA and a 16-wide dispatch). In order to support 8x MSAA, we must compute which sample is associated with each subspan, using the "Starting Sample Pair Index" field in the thread payload. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Properly adjust primitive size for 8x MSAA.Paul Berry2012-07-241-4/+17
| | | | | | | | | | | | | | When rendering to an IMS MSAA surface on Gen7, blorp sets up the rendering pipeline as though it were rendering to a single-sampled surface; accordingly it must adjust the size of the primitive it sends down the pipeline to account for the interleaving of samples in an IMS surface. This patch modifies the size adjustment code to properly handle 8x MSAA, which makes room for the extra samples by using an interleaving pattern that is twice as wide as 4x MSAA. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Parameterize manual_blend() by num_samples.Paul Berry2012-07-241-8/+5
| | | | | | | | | | | | This patch adds a num_samples argument to the blorp function manual_blend(), allowing it to be told how many samples need to be blended together. Previously it assumed 4x MSAA, since that was all we supported. We also bump up LOG2_MAX_BLEND_SAMPLES from 2 to 3, so that manual_blend() will be able to handle 8x MSAA. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Remove comment about falsely claiming to support MSAA.Paul Berry2012-07-241-5/+0
| | | | | | Gen6+ hardware now supports MSAA properly. Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Handle DrawBuffers properly.Paul Berry2012-07-241-7/+10
| | | | | | | | | | | | When the client program uses glDrawBuffer() or glDrawBuffers() to select more than one color buffer for drawing into, and then performs a blit, we need to blit into every single enabled draw buffer. +2 oglconforms. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50407 Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Rearrange order of blit validation and preparation steps.Paul Berry2012-07-241-55/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch rearranges the order of steps performed by a blorp blit from this: - Sync up state of window system buffers. - Find buffers. - Find miptrees. - Make sure buffer formats match. - Handle mirroring. - Make sure width and height match. - Handle clipping/scissoring. - Account for window system origin conventions. - Do depth resolves, if applicable. - Do the blit. - Record the need for a future HiZ resolve, if applicable. To this: - Sync up state of window system buffers. - Handle mirroring. - Make sure width and height match. - Handle clipping/scissoring. - Account for window system origin conventions. - Find buffers. - Make sure buffer formats match. - Find miptrees. - Do depth resolves, if applicable. - Do the blit. - Record the need for a future HiZ resolve, if applicable. The steps are the same, but they are now performed in an order that will make it possible to implement correct DrawBuffers support. Note that the last four steps are now in a separate function (do_blorp_blit), since they will need to be executed repeatedly when DrawBuffers support is added. Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Don't fall back to swrast when miptrees absent.Paul Berry2012-07-241-6/+2
| | | | | | | | | | | | | Previously, the blorp engine would fall back to swrast if the source or destination of a blit had no associated miptree. This was unnecessary, since _mesa_BlitFramebufferEXT() already takes care of making the blit silently succeed if there are no buffers bound, so the fallback paths could never actually happen in practice. Removing these fallback paths will simplify the implementation of correct DrawBuffers support in blorp. Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Fixup scissoring of blits to window system buffers.Paul Berry2012-07-241-12/+16
| | | | | | | | | | | | | This patch modifies the order of operations in the blorp engine so that clipping and scissoring are performed before adjusting the coordinates to account for the difference in origin convention between window system buffers and framebuffer objects. Previously, we would do clipping and scissoring after adjusting for origin conventions, so we would get scissoring wrong in window system buffers. Fixes Piglit test "fbo-scissor-blit window". Reviewed-by: Chad Versace <[email protected]>
* i965/blorp: Simplify check that src/dst width/height match.Paul Berry2012-07-241-4/+2
| | | | | | | | | | | When checking that the source and destination dimensions match, we don't need to store the width and height in variables; doing so just risks confusion since right after the check, we do clipping and scissoring, which may alter the width and height. No functional change. Reviewed-by: Chad Versace <[email protected]>
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