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* Merge branch 'mesa_7_6_branch'Brian Paul2009-10-281-0/+1
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| * intel: Fix memory leak in case of renderbuffer bad formatVinson Lee2009-10-281-0/+1
| | | | | | | | Signed-off-by: Brian Paul <[email protected]>
* | r600: add occlusion query supportAlex Deucher2009-10-284-10/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on initial patch from Stephan Schmid <[email protected]>. Basic idea is to dump the zpass count at the start and end of the query and subtract to get the total number of visible fragments. HW writes alternating qwords for up to 4 DBs. On the first pass, we start at buffer address + 0; on the second pass, we start at buffer address + 8 (bytes). The resulting buffer at the end of the query looks like: qw[0]: db0 start qw[1]: db0 end ... qw[6]: db3 start qw[7]: db3 end The MSB of each qword is the valid bit and the lower 63 bits are the zpass count for that DB. OQ on RV740 is disabled at the moment as it only seems to report results for half of its DBs. This needs further investigation. Signed-off-by: Alex Deucher <[email protected]>
* | Merge branch 'mesa_7_6_branch'Brian Paul2009-10-282-1/+9
|\| | | | | | | | | | | | | Conflicts: src/mesa/shader/lex.yy.c src/mesa/shader/program_lexer.l
| * intel: Fix memory leak in event of mip tree allocation failureVinson Lee2009-10-281-1/+3
| | | | | | | | Signed-off-by: Brian Paul <[email protected]>
| * intel: Fix flipped condition in ARB_sync GetSYnciv(GL_SYNC_STATUS).Eric Anholt2009-10-271-1/+1
| | | | | | | | | | Bug #24435 (cherry picked from commit d56125a298106d81e10674f1c4b3b43b51a5139d)
| * intel: added region draw_x/y offsets in x/y_tile_swizzle() funcsBrian Paul2009-10-271-0/+6
| | | | | | | | This fixes the second part of bug 23552.
| * intel: fix src offset bug in do_copy_texsubimage()Brian Paul2009-10-271-1/+1
| | | | | | | | | | | | Use src->draw_offset intead of zero. Zero usually worked, except when the src renderbuffer is actually a texture mipmap level higher than zero. Fixes progs/test/blitfb.c test.
| * i915: Fix driver for the miptree x/y offset changes.Eric Anholt2009-10-272-6/+20
| | | | | | | | Bug #24734.
| * i965: be clear that the Fallback field is a boolean, not a bitfieldBrian Paul2009-10-273-4/+8
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| * Revert "i965: fix hacked Fallback usage in brw_prepare_vertices()"Brian Paul2009-10-272-6/+2
| | | | | | | | | | | | | | | | | | This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c. It turns out the i965 driver uses the intel->Fallback field as a boolean, not as a bitmask. The intelFallback() function is a no-op in the i965 driver. It would have been nice if there were some comments about this. I'll fix that next...
| * intel: fix GL state bugs in intel_texture_bitmap()Brian Paul2009-10-261-4/+3
| | | | | | | | | | | | | | Need to push texture state and polygon state too. Fixes rendering glitches seen in progs/demos/engine when changing the rendering mode (wireframe, texture modes). This makes bitmap rendering a little slower, unfortunately.
* | intel: silence warningBrian Paul2009-10-271-0/+1
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* | via: silence unused var warningsBrian Paul2009-10-272-2/+2
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* | intel: minor clean-up, commentsBrian Paul2009-10-271-2/+3
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* | intel: use _mesa_get_current_tex_unit() helperBrian Paul2009-10-271-9/+6
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* | mesa: s/Bilt/BlitBrian Paul2009-10-271-1/+1
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* | intel: fix comment, formattingBrian Paul2009-10-271-2/+2
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* | intel: fix src offset bug in do_copy_texsubimage()Brian Paul2009-10-271-1/+1
| | | | | | | | | | | | Use src->draw_offset intead of zero. Zero usually worked, except when the src renderbuffer is actually a texture mipmap level higher than zero. Fixes progs/test/blitfb.c test.
* | i915: Fix driver for the miptree x/y offset changes.Eric Anholt2009-10-272-4/+20
| | | | | | | | Bug #24734.
* | i965: be clear that the Fallback field is a boolean, not a bitfieldBrian Paul2009-10-273-4/+8
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* | Revert "i965: fix hacked Fallback usage in brw_prepare_vertices()"Brian Paul2009-10-272-6/+2
| | | | | | | | | | | | | | | | | | This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c. It turns out the i965 driver uses the intel->Fallback field as a boolean, not as a bitmask. The intelFallback() function is a no-op in the i965 driver. It would have been nice if there were some comments about this. I'll fix that next...
* | intel: fix GL state bugs in intel_texture_bitmap()Brian Paul2009-10-271-4/+3
| | | | | | | | | | | | | | Need to push texture state and polygon state too. Fixes rendering glitches seen in progs/demos/engine when changing the rendering mode (wireframe, texture modes). This makes bitmap rendering a little slower, unfortunately.
* | Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt2009-10-238-122/+120
|\| | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_fbo.c src/mesa/drivers/dri/intel/intel_mipmap_tree.c src/mesa/drivers/dri/intel/intel_mipmap_tree.h src/mesa/drivers/dri/intel/intel_tex_copy.c src/mesa/drivers/dri/intel/intel_tex_image.c
| * intel: Keep track of x,y offsets in miptrees and use them for blitting.Eric Anholt2009-10-238-140/+118
| | | | | | | | | | | | | | | | | | By just using offsets, we confused the hardware's tiling calculations, resulting in failures in miptree validation and blit clears. Fixes piglit fbo-clearmipmap. Bug #23552. (automatic mipmap generation)
* | i965: Annotate _NEW_COLOR dependency for brw_update_renderbuffer_surface().Eric Anholt2009-10-231-1/+2
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* | mesa/dri: Remove extension_helper.h.Chia-I Wu2009-10-231-6647/+0
| | | | | | | | Signed-off-by: Chia-I Wu <[email protected]>
* | mesa: Enable remap table in core.Chia-I Wu2009-10-2325-465/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | This enables the remap table in core. driInitExtensions is adapted to use the remap table. All uses of extension_helper.h are replaced by remap_helper.h. The chicken-egg problem of the DRI drivers is also solved. It is now also possible to pass NULL extensions to driInitExtensions. It will cause driInitExtensions to map all known functions. This functionality is used by software drivers and EGL_i915. Signed-off-by: Chia-I Wu <[email protected]>
* | r600: remove duplicate stride settingAndre Maasikas2009-10-231-4/+0
| | | | | | | | | | Stride is set already in r700SetVertexFormat and there it works correctly for 0 also
* | r600: for position invariant programs reading vert_pos is not always known ↵Andre Maasikas2009-10-231-0/+5
| | | | | | | | at this point
* | r600: remove remains of old tnl pipelineAlex Deucher2009-10-237-268/+41
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* | r600: fix render size predictionAlex Deucher2009-10-233-20/+20
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* | r600: remove old tnl pipelineAlex Deucher2009-10-232-192/+34
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* | r600: clean up context creationAlex Deucher2009-10-231-102/+100
| | | | | | | | Make it more consistent with other radeon drivers.
* | Merge branch 'mesa_7_6_branch'Brian Paul2009-10-225-11/+37
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| * intel: flush old context before binding new contextBrian Paul2009-10-221-2/+15
| | | | | | | | | | Per the GLX spec, when changing rendering contexts, the old context should first be flushed.
| * i965: fix hacked Fallback usage in brw_prepare_vertices()Brian Paul2009-10-222-2/+6
| | | | | | | | | | | | | | | | Setting intel->Fallback = 1 clobbered any fallback state that was already set. Not sure where this hack originated (the git history is a little convoluted). Define and use a new BRW_FALLBACK_DRAW bit instead. This shouldn't break anything and could potentially fix some bugs (but no specific ones are known).
| * intel: define INTEL_FALLBACK_DRIVER for driversBrian Paul2009-10-221-0/+1
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| * intel: Fallback field is a bitmask, use GLbitfieldBrian Paul2009-10-223-5/+14
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| * i965: remove unused brw_context::tmp_fallback fieldBrian Paul2009-10-221-1/+0
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| * i965: remove unused BRW_FALLBACK_TEXTURE bitBrian Paul2009-10-221-1/+1
| | | | | | | | | | The value was probably wrong too. It was the same as INTEL_FALLBACK_DRAW_BUFFER.
* | Kill off trident.Corbin Simpson2009-10-229-2988/+0
| | | | | | | | | | Hm. I could have said "chew trident and spit it out," or perhaps "spear trident," instead. Dohoho.
* | Nuke s3v.Corbin Simpson2009-10-2228-7719/+1
| | | | | | | | As per FDO #17889.
* | Merge branch 'mesa_7_6_branch' of ↵Alex Deucher2009-10-223-7/+77
|\| | | | | | | git+ssh://[email protected]/git/mesa/mesa
| * r600: set barrier for tex inst if dst is used earlier, might overwrite it ↵Andre Maasikas2009-10-221-2/+25
| | | | | | | | otherwise
| * r600: need to export something from PSAndre Maasikas2009-10-222-2/+19
| | | | | | | | | | | | | | Also avoids empty shader for "END" - seems to be somewhat valid fp Maybe this can be done differently in the future (fake FRAG_RESULT_COLOR already in Map_Fragment_Program() or is there a way to program the chip to not hang in case of no exports.
| * r600: add beginnings of ARL instructionAndre Maasikas2009-10-222-3/+33
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* | intel: Fix flipped condition in ARB_sync GetSYnciv(GL_SYNC_STATUS).Eric Anholt2009-10-201-1/+1
| | | | | | | | Bug #24435
* | meta: Fix the BufferSubData in meta clear to be BufferData.Eric Anholt2009-10-201-3/+2
| | | | | | | | | | Fixes a 3.4% +/- 1.3% performance regression in my GL demo (n=3). The other meta code could probably also use the same treatment.
* | Merge branch 'mesa_7_6_branch' of ↵Alex Deucher2009-10-197-33/+51
|\| | | | | | | | | | | git+ssh://[email protected]/git/mesa/mesa regenerated lex.yy.c
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