summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers
Commit message (Collapse)AuthorAgeFilesLines
* i965: Move fs_visitor ra pass to new fs_visitor::allocate_registers()10.4-branchpointKristian Høgsberg2014-11-142-59/+69
| | | | | | | | | This will be reused for the scalar VS pass. v2 (Ken): Rebase on master. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move fs_visitor optimization pass into new method fs_visitor::optimize()Kristian Høgsberg2014-11-142-65/+72
| | | | | | | We'll reuse this toplevel optimization driver for the scalar VS. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move more code into codegen-branch of the fs_visitor::run() if statementKristian Høgsberg2014-11-141-12/+11
| | | | | | | | | | | | | These last few operations all only apply when we've actually generated code, optimized and allocated registers. The dummy and the repclear shaders don't need the gen4 send workaround, and don't spill. This means we can move these lines into the else-branch, which will make the following refactoring easier. v2 (Ken): Rebase on master, which removed the uncompressed stack. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Refactor fs_generator APIKristian Høgsberg2014-11-144-39/+23
| | | | | | | | | | | | We split out SIMD8 and SIMD16 generation into seperate calls to new method generate_code(), which returns the start offset for the generated code. A new get_assembly() method returns the generated code. This avoids asserting MESA_SHADER_FRAGMENT and accessing wm_prog_data in the generator. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/dri: Support EGL_CONTEXT_OPENGL_DEBUG_BIT_KHR/GLX_CONTEXT_DEBUG_BIT_ARB ↵José Fonseca2014-11-141-8/+6
| | | | | | | | | | | | | on ES contexts. The latest version of the specs explicitly allow it, and given that Mesa universally supports KHR_debug we should definitely support it. Totally untested. (Just happened to noticed this while implementing GLX_EXT_create_context_es2_profile for st/xlib.) Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/vec4: Combine all the math emitters.Kenneth Graunke2014-11-132-104/+17
| | | | | | | | | | | 17 insertions(+), 102 deletions(-). Works just as well. v2: Make emit_math take const references (suggested by Matt), drop redundant WRITEMASK_XYZW setting (Matt and Curro). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/vec4: Use const references in emit() functions.Kenneth Graunke2014-11-132-15/+14
| | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Use macros to create prototypes for emitter helpers.Kenneth Graunke2014-11-131-57/+41
| | | | | | | | We do this almost everywhere else; this should make it easier to modify. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Always enable VF statisticsBen Widawsky2014-11-131-2/+1
| | | | | | | | | | | | | | | Every other unit in the geometry pipeline automatically enables statistics gathering. This part of the pipe has been controlled by the DEBUG_STATS variable, but this is asymmetric. This dates back to the original implementation, and I am not sure if there is a reason for it. I need access to these stats to implement ARB_pipeline_statistics_query. Eric wrote it, and Ken touched it last. Do you have any opposition? Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86145 Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Ben Widawsky <[email protected]>
* i915: Emit 3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLEVille Syrjälä2014-11-136-17/+17
| | | | | | | | | | | | | | | According to gen2 BSpec the pipeline must be flushed at least up to the windower before changing the scissor rect enable field. Emitting the 3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE is sufficient to do that. gen3 BSpec no longer has that piece of text, but let's make the same change there too for symmetry. The spec does still say that the scissor rectangle must be defined before enabling it, so the new order does seem more in line with the spec. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i915: Don't call _mesa_meta_glsl_Clear() on gen2Ville Syrjälä2014-11-131-1/+1
| | | | | | | | | | | | | | | | | Gen2 doesn't have fragment shaders so we shouldn't be calling _mesa_meta_glsl_Clear() on gen2. Restore the appropriate ARB_fragment_shader check to the clear path which was lost in: commit 94f22fbe787214580a1a13a774114d2650c166cb Author: Tapani Pälli <[email protected]> Date: Wed Aug 8 20:46:45 2012 +0300 intel: use _mesa_meta_Clear with OpenGL ES 1.1 v2 v2: Fix spelling in commit message Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i915: Protect macro argument for TEXTURE_SET()Ville Syrjälä2014-11-131-1/+1
| | | | | | | | | | TEXTURE_SET() is the only register macro that forgets to wrap the argument evaluation in parens. Only simple integers are passed to this macro so there's no bug but sitll it seems prudent to add the parens. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i915: Kill intel_context::hw_stencilVille Syrjälä2014-11-132-2/+0
| | | | | | | ctx.hw_stencil is not used anywhere so kill it. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i915: Accept GL_DEPTH_STENCIL GL_DEPTH_COMPONENT formats for renderbuffersVille Syrjälä2014-11-131-0/+9
| | | | | | | | | | | | | | | | | | Gen2 doesn't support depth/stencil textures, and since commit c1d4d4999303f9167b20f4e0674b9436e6295cf7 Author: Ville Syrjälä <[email protected]> Date: Thu Apr 24 14:11:43 2014 +0300 i915: Don't advertise Z formats in TextureFormatSupported on gen2 depth/stencil formats are no longer accepted as texture formats. However we still want depth/stencil renderbuffers, so add explicit format checks to intel_alloc_renderbuffer_storage() to allow such things. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i915: Override mip filter to nearest with anisoVille Syrjälä2014-11-131-0/+2
| | | | | | | | | | gen2 doesn't supporte linear mip filter with anisotropic min/mag filtering. The hardware would automagically downgrade the min/mag filters to linear in such cases, which IMO looks worse than forcing the mip filter to nearest. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i915: Use L8A8 instead of I8 to simulate A8 on gen2Ville Syrjälä2014-11-132-3/+2
| | | | | | | | | | | | | | | | Gen2 doesn't support the A8 texture format. Currently the driver substitutes it with I8, but that results in incorrect RGB values. Use A8L8 instead. We end up wasting a bit of memory, but at least we should get the correct results. v2: Handle the fallback in _mesa_choose_tex_format() and also do it for all alpha formats that currently accept A8 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72819 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80050 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38873 Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i915: Fix GL_DOT3_RGBA a bitVille Syrjälä2014-11-131-2/+3
| | | | | | | | | | | | | The spec says using DOT4 for alpha is undefined unless DOT4 is also used for color. It seems to do the right thing anyway, but better safe than sorry. Also override numAlphaArgs to 2 for DOT4 since that's what it wants. This migth fix something in case the specified alpha mode has only one argument. Also avoids emitting a needless 3DSTATE_MAP_BLEND_ARG if the specified alpha mode has three arguments. Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i965/cfg: Remove if_block/else_block.Matt Turner2014-11-113-30/+1
| | | | | | | | I used these in the SEL peephole, but they require extra tracking and fix ups. The SEL peephole can pretty easily find the blocks it needs without these. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Don't use if_block/else_block in SEL peephole.Matt Turner2014-11-111-6/+11
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Advertise a line width of 40.0 on Cherryview and Skylake.Kenneth Graunke2014-11-081-1/+5
| | | | | | | | | According to the documentation, line widths higher than 40.0 may have quality problems. That's already 20 times larger than we've been exposing, so it seems totally sufficient. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Advertise larger line widths.Kenneth Graunke2014-11-081-3/+9
| | | | | | | | | | | | | | | | We've artificially been limiting this to 5 for no particular reason. On Gen4-5, the limit is [0, 7.5] with a granularity of 0.5 (U3.1). On Gen6+, the limit is [0, 7.9921875]. Since it's a U3.7, the granularity should be 0.125 (1/8). This patch conservatively advertises one granularity smaller than the hardware's maximum value, just in case there's a problem using the largest possible value. On Gen4-5, this is 7.5 - 0.5 = 7.0. On Gen6+, this is 8.0 - 0.125 = 7.875. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Use ctx->Const.MaxLineWidth when clamping ctx->Line.Width.Kenneth Graunke2014-11-084-5/+8
| | | | | | | | | | | | Rather than hardcoding platform values in every code path, just use the maximum value we set. Currently, ctx->Const.LineWidth == 5, which is smaller than the hardware limit. But applications shouldn't be using a value larger than we support anyway. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Set Line Width correctly on Cherryview and Skylake.Kenneth Graunke2014-11-082-1/+6
| | | | | | | Line Width moved to DW1 bits 29:12. It's actually now a U11.7. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: drop the custom gen8_instruction CFLAGEmil Velikov2014-11-071-2/+0
| | | | | | | | | | | | | | | No longer needed as the file was removed with commit 8c229d306b3f312adbdfbaf79967ee43fbfc839e Author: Kenneth Graunke <[email protected]> Date: Mon Aug 11 10:07:07 2014 -0700 i965: Delete the Gen8 code generators. We now use the brw_eu_emit.c code instead. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965/fs: Wire up control flow correctly in predicated break pass.Matt Turner2014-11-061-3/+7
| | | | | | | | When the earlier block ended with control flow, we'd mistakenly remove some of its links to its children. The same happened with the later block. Acked-by: Jason Ekstrand <[email protected]>
* i965/cfg: Add functions to get first and last non-CF instructions.Matt Turner2014-11-061-0/+74
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Remove non-existent vertical strides from array.Matt Turner2014-11-061-1/+1
| | | | | | These never existed, as far as I can tell. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert stride/width/execution size macros into enums.Matt Turner2014-11-061-28/+33
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove force uncompressed stack.Matt Turner2014-11-063-27/+0
| | | | | | Last use was in shader_time. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Use execution size of 1 for some shader_time operations.Matt Turner2014-11-061-1/+1
| | | | | | The ADDs depended on dispatch_width, which really isn't what we wanted. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Use mov(4) instructions to read timestamp.Matt Turner2014-11-061-5/+4
| | | | We only want fields 0-2.
* Releasing a surfaceless EGL context doesn't release underlying DRI context.Alexandros Frantzis2014-11-061-2/+6
| | | | | | | | | | | | | | | | | | driUnbindContext() checks for valid drawables before calling the driver unbind function. In case of Surfaceless contexts, the drawables are always Null and we end up not releasing the underlying DRI context. Moving the call to the driver function before the drawable validity checks fixes things. Steps to trigger this bug are following: - create surfaceless context and make it current - make some other context current - {another thread} destroy surfaceless context - make another context current Signed-off-by: Alexandros Frantzis <[email protected]> Signed-off-by: Kalyan Kondapally <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74563
* i965: Fix sampler state pointer adjustment for nonconst samplersChris Forbes2014-11-051-1/+1
| | | | | | | | | | | This started hitting an assertion recently. Only affects Haswell (Ivybridge doesn't support this meddling with the sampler state pointer, and ARB_gpu_shader5 is not enabled yet on Broadwell) 14 Piglits crash->pass. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Re-enable Z16 on Gen8+.Kenneth Graunke2014-11-041-0/+7
| | | | | | | | | | | | | Improves performance in GLBenchmark 2.7 TRex by 3.88889% +/- 0.336383% (n=80) at 1280x720 on Broadwell GT3. Together with the previous patch, it improves performance by 5.42738% +/- 0.541971% (n=10) at 1920x1080. Note that without the PMA stall fix, this would instead decrease performance by 22%. v2: Update comment (noticed by Kristian Høgsberg). Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Implement the PMA stall fix.Kenneth Graunke2014-11-044-0/+180
| | | | | | | | | | | | | | | | | | | Certain non-promoted depth cases typically incur stalls. In very specific cases, we can enable a workaround which improves performance. Improves performance in GLBenchmark 2.7 TRex by 1.17762% +/- 0.448765% (n=75) at 1280x720 on Broadwell GT3. Haswell has this feature as well, but we can't currently write registers from userspace batches (and we'd incur additional software batch scanning overhead as well), so we haven't enabled it. Broadwell allows us to write CACHE_MODE_1. Backporters beware: the formula and flushing incantation differs between Haswell and Broadwell. v2: Move pma_stall_bits from brw->state to brw itself (requested by Kristian Høgsberg). Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Add #defines for Broadwell HiZ workarounds in CACHE_MODE_1.Kenneth Graunke2014-11-041-0/+6
| | | | | | This patch adds macros needed for the HiZ PMA stall optimization. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Update compaction code to handle Skylake like Cherryview.Kenneth Graunke2014-11-031-4/+4
| | | | | | | | | Matt requested this in review feedback on the original patch, which I completely missed when pushing this series. Kristian also made this change, but I grabbed the wrong version of the patch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Disable fast color clears on Skylake for now.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | We're not programming the clear values yet, so this won't work. This patch should be (effectively) reverted eventually. Signed-off-by: Kenneth Graunke <[email protected]>
* i965/skl: Use new MOCS for SKLKristian Høgsberg2014-11-036-17/+33
| | | | | | | | | | | | On Skylake, the MOCS bits are an index into a table of 63 different, configurable cache configurations. As for previous GENs, we only care about WB and WT, which are available in the documented default set. Define SKL_MOCS_WB and SKL_MOCS_WT to the indices for those configucations and use those for the Skylake MOCS values. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Implement workaround for VF Invalidate issueJordan Justen2014-11-031-0/+9
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Update Viewport Z Clip Test Enable bits for Skylake.Kenneth Graunke2014-11-032-2/+10
| | | | | | | | | Skylake has separate controls for enabling the Z Clip Test for the near and far planes. For now, maintain the legacy behavior by setting both. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Emit extra zeros in 3DSTATE_DS on Skylake.Kenneth Graunke2014-11-031-10/+5
| | | | | | | | | Skylake's 3DSTATE_DS packet has a few more fields; we don't support domain shaders yet though. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Init instructions compaction tables for SKLKristian Høgsberg2014-11-031-0/+1
| | | | | | | They are the same as for BDW, so just add a case for SKL to the init switch. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/skl: Add fast clear resolve rect multipliers for SKLKristian Høgsberg2014-11-031-2/+5
| | | | | | | | SKL updates the resolve rectangle scaling factors again. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Always emit 3DSTATE_BINDING_TABLE_POINTERS_* on Skylake.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | | | | On SKL, 3DSTATE_CONSTANT_* command is not committed until we give the corresponding 3DSTATE_BINDING_TABLE_POINTERS_* command. If we fail to do so, the constant buffers wont be read and push constants will be wrong. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Allocate 16 DWords for SURFACE_STATE on Skylake.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | | Otherwise they overlap and horrible things happen. All the new DWords are for fast color clear values, which we don't do yet. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Refactor surface state allocation.Kenneth Graunke2014-11-031-10/+16
| | | | | | | | | | We will need to allocate more DWords on Skylake. v2: Don't mark brw_context parameter const. It's modified. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on Skylake.Kenneth Graunke2014-11-031-2/+11
| | | | | | | | | Skylake introduces a new base address for a feature we don't yet expose. Setting these to 0 should be safe. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Update stencil reference handling for Skylake.Kenneth Graunke2014-11-033-6/+28
| | | | | | | | | Skylake uploads the stencil reference values in DW3 of the 3DSTATE_WM_DEPTH_STENCIL packet, rather than in COLOR_CALC_STATE. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Set mask bits in PIPELINE_SELECT on Skylake.Kenneth Graunke2014-11-031-1/+1
| | | | | | | | | | | Skylake has some extra bits in PIPELINE_SELECT, none of which are interesting for a 3D driver. In order to selectively change them, it also introduces new "mask bits" in 15:8. We care about the "Pipeline Selection" bits (1:0), so set the mask to 0x3. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-01 23:36:54 +0000