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* i965: Enable resource streamer for the batchbufferAbdiel Janulgue2015-07-187-2/+36
* i965: Define HW-binding table and resource streamer control opcodesAbdiel Janulgue2015-07-182-0/+33
* i965/fs: don't make unused payload registers interfereConnor Abbott2015-07-171-1/+6
* i965/fs: remove special case in setup_payload_interference()Connor Abbott2015-07-171-20/+0
* i965/fs: Mark last used ip for all regs read in the payloadJordan Justen2015-07-171-1/+4
* i965/fs: fix regs_read() for LINTERPConnor Abbott2015-07-171-1/+2
* i965/cs: Use dispatch width of 8 for cs terminate payload setupJordan Justen2015-07-161-1/+1
* i965/cs: Return 1 for regs_read on CS_OPCODE_CS_TERMINATEJordan Justen2015-07-161-0/+3
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-167-47/+51
* Revert "i965: Push miptree tiling request into flags"Ben Widawsky2015-07-167-51/+47
* i965: Push miptree tiling request into flagsBen Widawsky2015-07-167-47/+51
* i965/fs: Factor out universally broken calculation of the register component ...Francisco Jerez2015-07-164-12/+23
* i965: Implement nir_op_uadd_carry and _usub_borrow without accumulator.Francisco Jerez2015-07-163-35/+12
* i965: Implement b2f and b2i using negation.Francisco Jerez2015-07-162-9/+2
* i965/gen9: Use custom MOCS entries set up by the kernel.Francisco Jerez2015-07-162-7/+7
* r200: fix some potential big endian issuesRoland Scheidegger2015-07-165-129/+140
* radeon: fix some potential big endian issuesRoland Scheidegger2015-07-164-90/+76
* radeon/r200: mark state atoms as dirty after blitsRoland Scheidegger2015-07-162-0/+24
* r200: fix fbo rendering by disabling optimized texture format chooserRoland Scheidegger2015-07-161-1/+13
* i965: Fix 32 bit build warnings in intel_get_yf_ys_bo_size()Anuj Phogat2015-07-151-3/+3
* i965: Optimize batchbuffer macros.Matt Turner2015-07-156-42/+70
* i965: Add and use USED_BATCH macro.Matt Turner2015-07-156-22/+25
* i965: Split batch emission from relocation functions.Matt Turner2015-07-152-34/+30
* i965: Move BEGIN_BATCH() into same control flow as ADVANCE_BATCH().Matt Turner2015-07-151-2/+2
* osmesa: fix OSMesaPixelsStore typoBrian Paul2015-07-151-1/+1
* i965/cs: Initialize GPGPU Thread CountJordan Justen2015-07-142-0/+25
* i965: Mark constant static data as const.Matt Turner2015-07-142-23/+23
* mesa: rename is_in_uniform_block to is_in_buffer_blockIago Toral Quiroga2015-07-141-1/+1
* radeon: remove dri_mirror stateEmil Velikov2015-07-134-31/+15
* i915: remove unused driFd variableEmil Velikov2015-07-132-3/+0
* i965: bump libdrm requirement to 2.4.61 and drop in-tree workaroundEmil Velikov2015-07-131-5/+0
* i965: Remove special case for layered drawbuffer attachments.Kenneth Graunke2015-07-101-1/+2
* i965/gen6: Set up layer constraints properly for depth buffers.Kenneth Graunke2015-07-101-1/+5
* i965: Label the repclear shader "meta repclear" rather than "meta clear".Kenneth Graunke2015-07-101-1/+1
* i965: Fix indentation in emit_control_data_bits().Kenneth Graunke2015-07-101-72/+70
* i965/gs: Move vertex_count != 0 check up a level; skip one caller.Kenneth Graunke2015-07-101-6/+8
* i965/vs: Get rid of brw_vs_compile completely.Kenneth Graunke2015-07-093-40/+31
* i965/vs: Remove 'c'/vs_compile from vec4_vs_visitor.Kenneth Graunke2015-07-094-15/+15
* i965/vec4: Move c->last_scratch into vec4_visitor.Kenneth Graunke2015-07-098-22/+15
* i965/vec4: Move total_scratch calculation into the visitor.Kenneth Graunke2015-07-093-10/+7
* i965/vec4: Move perf_debug about register spilling into the visitor.Kenneth Graunke2015-07-093-11/+13
* i965/vec4: Plumb log_data through so the backend_shader field gets set.Kenneth Graunke2015-07-098-8/+18
* i965: Switch on shader stage in nir_setup_outputs().Kenneth Graunke2015-07-091-26/+33
* i965: Set brw->batch.emit only #ifdef DEBUG.Matt Turner2015-07-092-1/+3
* i965/hsw: Implement end of batch workaroundBen Widawsky2015-07-092-2/+29
* i965: Move pipecontrol workaround bo to brw_pipe_controlChris Wilson2015-07-086-37/+64
* i965: Query whether we have kernel support for the TIMESTAMP register onceChris Wilson2015-07-083-5/+25
* i965/vs: Fix matNxM vertex attributes where M != 4.Kenneth Graunke2015-07-071-4/+11
* i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.Francisco Jerez2015-07-071-7/+1
* i965/gen4-5: Program the execution size correctly for DO/WHILE instructions.Francisco Jerez2015-07-071-1/+1
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