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* mesa: Update gl_scissor_attrib to support ARB_viewport_arrayCourtney Goeltzenleuchter2014-01-2011-38/+46
| | | | | | | | | | | | | | | | | | Update Mesa and drivers to access updated gl_scissor_attrib. Now have an enable bitfield and array of gl_scissor_rects. Drivers have been updated to the new scissor enable state attribute (gl_context.scissor.EnableFlags) but still treat it as a single boolean which is okay as mesa will only use bit 0 when communicating with a driver that does not support ARB_viewport_array. v2 (idr): Rebase fixes. v3 (idr): Small code formatting fix suggsted by Ken. Signed-off-by: Courtney Goeltzenleuchter <[email protected]> Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i915,r200,radeon,vega: Change vendor from "VMware, Inc." to "Mesa Project".José Fonseca2014-01-202-2/+2
| | | | | | | | | | These are components which were originally developed by Tungsten Graphics, which was in turn acquired by VMware, but are de facto now being maintained by third-party contributors of the Mesa open-source community. This matches what's reported by swrast driver and a few other components. Suggested by Ian Romanick.
* i965/blorp: reduce the scope of the explicit compression controlTopi Pohjolainen2014-01-201-11/+20
| | | | | | | | | | | | | | By highlighting these special cases makes it clearer to switch to the fs-generator as the wider scoped compression control settings used in the current implementation can be simply dropped. No regressions on IVB (piglit quick + unit tests). v2 (Ian): typo in a comment Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: remove dependency to compression control stateTopi Pohjolainen2014-01-201-4/+3
| | | | | | | | | | | | | | | | | | | | Effectively only the mask control bit gets altered for the single addition in question and hence there is no real need to use a fresh state control level for it -- that is more useful when multiple intructions share the same mask and compression settings. This is a preparation step for removing the explicit compression control modifiers in the blit compiler. After this patch there are no nested state control levels making the constant nature of the compression settings more apparent. No regressions on IVB (piglit quick + unit tests). v2 (Matt, Ian): use temporary variable instead of assigning directly on the same line with a function call. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Only update renderbuffers on initial intelMakeCurrentKristian Høgsberg2014-01-191-1/+8
| | | | | | | | | | | | | | | | | We call intel_prepare_render() in intelMakeCurrent() to make sure we have renderbuffers before calling _mesa_make_current(). The only reason we do this is so that we can have valid defaults for width and height. If we already have buffers for the drawable we're making current, we don't need this step. In itself, this is a small optimization, but it also avoids a round trip that could block on the display server in a unexpected place. https://bugs.freedesktop.org/show_bug.cgi?id=72540 https://bugs.freedesktop.org/show_bug.cgi?id=72612 Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Double the push constant space multipliers on Broadwell too.Kenneth Graunke2014-01-181-2/+4
| | | | | | | Broadwell has 2Kb push constant size increments like Haswell GT3. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Update invariant state for Broadwell.Kenneth Graunke2014-01-181-4/+12
| | | | | | | | The only difference is that STATE_SIP takes a 48-bit address, so we need to output two zeroes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use the Sandybridge VUE format on Broadwell as well.Kenneth Graunke2014-01-181-0/+1
| | | | | | | It hasn't changed. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Create a new fragment shader backend for Broadwell.Kenneth Graunke2014-01-184-5/+1100
| | | | | | | | | | | | | | | | | | | | | | | | This replaces the old fs_generator backend. v2: Port to the C-based representation of assembly instructions. Fix texturing after the texture-grf merge. v3: Add high quality derivative support. Fix SET_SIMD4X2_OFFSET. v4: Pass brw_context to gen8_instruction functions as required. v5: Fixes for MRT, as well as zero render targets (alpha test only). v6: Replace n-wide with SIMDn in comments and messages; port over Topi's blorp-generator changes; add missing TXF_MCS opcode, fix missing high quality derivatives for DDX; fix typo (all caught by Eric). Simplify ADDC/SUBB handling; drop "Used only on Gen6+" comment (caught by Matt). Emit SIMD16 versions of three source instructions (caught by both Eric and Matt). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Create a new vec4 backend for Broadwell.Kenneth Graunke2014-01-185-17/+976
| | | | | | | | | | | | | | | | | | | | This replaces the old vec4_generator backend. v2: Port to use the C-based instruction representation. Also, remove Geometry Shader offset hacks - the visitor will handle those instead of this code. v3: Texturing fixes (including adding textureGather support). v4: Pass brw_context to gen8_instruction functions as required. v5: Add SHADER_OPCODE_TXF_MCS support; port DUAL_INSTANCED gs fixes (caught by Eric). Simplify ADDC/SUBB handling; add comments to gen8_set_dp_message calls (suggested by Matt). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add a new infrastructure for generating Broadwell shader assembly.Kenneth Graunke2014-01-183-0/+842
| | | | | | | | | | | | | | | | | | | | | | | | | This replaces the brw_eu_emit.c layer for Broadwell. It will be used by both the vector and scalar shader backends. v2: Port to use the C-based instruction representation. v3: Fix destination register type for CMP. v4: Pass brw to gen8_instruction functions (required by rebase). v5: Remove bogus assertion on math instructions (caught by Piglit). v6: Remove more restrictions on math instructions (caught by Eric). Make ADDC and SUBB helpers set accumulator writes, like MAC and MACH (caught by Matt). v7: Don't implicitly force ALU3 operations to SIMD8 (we've been able to do SIMD16 versions since Haswell, but didn't when I originally wrote this code). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Implement a disassembler for Broadwell's new instruction encoding.Kenneth Graunke2014-01-182-0/+932
| | | | | | | | | | | | | | | | | | | | | Heavily based on Keith Packard's existing brw_disasm.c code. I've tried to go through most of the pieces (like SFIDs) and update the lists to include features added in recent generations. v2: Port to use the C-based instruction emitters. This allows us to use C99 array initializers, which tidies up some of the code. v3: Improve decoding of render target write messages. v4: Update for BRW_REGISTER_TYPE becoming an abstraction. v5: Rebase on Chris Forbes' SFID message defines. v6: Fix disassembly of UV immediates; remove silly casts. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add a new representation for Broadwell shader instructions.Kenneth Graunke2014-01-184-0/+835
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Broadwell significantly changes the EU instruction encoding. Many of the fields got moved to different bit positions; some even got split in two. With so many changes, it was infeasible to continue using struct brw_instruction. We needed a new representation. This new approach is a bit different: rather than a struct, I created a class that has four DWords, and helper functions that read/write various bits. This has several advantages: 1. We can create several different names for the same bits. For example, conditional modifiers, SFID for SEND instructions, and the MATH instruction's function opcode are all stored in bits 27:24. In each situation, we can use the appropriate setter function: set_sfid(), set_math_function(), or set_cond_modifier(). This is much easier to follow. 2. Since the fields are expressed using the original 128-bit numbers, the code to create the getter/setter functions follows the table in the documentation very closely. To aid in debugging, I've enabled -fkeep-inline-functions when building gen8_instruction.c. Otherwise, these functions cannot be called by gdb, making it insanely difficult to print out anything. Kenneth Graunke wrote most of this code. Damien Lespiau ported it to C99. Xiang Haihao added media fields. Zhao Yakui added indirect addressing support. Eric Anholt added an assertion to make sure that values fit in the alloted number of bits. v2: Update for brw_reg_type_to_hw_type(), which necessitates passing brw_context pointers around everywhere. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Damien Lespiau <[email protected]> Signed-off-by: Xiang, Haihao <[email protected]> Signed-off-by: Zhao Yakui <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Acked-by: Matt Turner <[email protected]>
* i965: Add SFID #defines for media stuff.Kenneth Graunke2014-01-181-0/+2
| | | | | | | | While we probably won't ever use these, having them makes it easy to share disassembler code between intel-gpu-tools and Mesa. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add #defines for new Broadwell math functions.Kenneth Graunke2014-01-181-0/+2
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: add struct and SFID for pixel interpolator messagesChris Forbes2014-01-182-0/+22
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/Gen7: Only emit cube face enables for cubes.Chris Forbes2014-01-191-2/+5
| | | | | | | | | This is not observed to actually fix anything, but the PRM says this field must be zero for other surface types. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Improve dumping of Gen7 SURFACE_STATEChris Forbes2014-01-191-6/+12
| | | | | | | | | Previously this was missing many interesting fields. Having them decoded makes debugging views much easier. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Add masks for more SURFACE_STATE fieldsChris Forbes2014-01-191-0/+2
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Remove CACHED_BATCH support altogether.Kenneth Graunke2014-01-176-53/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Using an unoptimized variant of glamor spending 50% of its CPU time in brw_draw_prims() (and hitting the cache *very* frequently): N Min Max Median Avg Stddev x 200 29200 40500 34900 34750 958.43256 + 200 31000 40300 34700 34622 916.35941 No difference proven at 95.0% confidence Similarly, no difference on GLB2.7: N Min Max Median Avg Stddev x 63 64.1 71.36 70.69 70.113175 1.6782026 + 63 63.6 71.18 70.75 70.223651 1.6044186 No difference proven at 95.0% confidence v2: Rebase on master (by anholt) v3: Add a missing BEGIN_BATCH(3) to aa_line_parameters -- CACHED_BATCH didn't have the asserts about batchbuffer usage that ADVANCE_BATCH does, so we started assertion failing. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Replace 8-wide and 16-wide with SIMD8 and SIMD16.Eric Anholt2014-01-176-44/+44
| | | | | | | | Those are the terms used in the docs, and think "n-wide" was something I just happened to say. Note that shader-db needs updating for the INTEL_DEBUG=fs parsing. Reviewed-by: Ian Romanick <[email protected]>
* i965: Stop doing our optimization on a copy of the GLSL IR.Eric Anholt2014-01-175-40/+28
| | | | | | | | | | | The original intent was that we'd keep a driver-private copy, and there would be the normal copy for swrast to make use of without the tuning (or anything more invasive we might do) specific to i965. Only, we don't generate swrast code any more, because swrast can't render current shaders anyway. Thus, our private copy is rather a waste, and we can just do our backend-specific operations on the linked shader. Reviewed-by: Ian Romanick <[email protected]>
* s/Tungsten Graphics/VMware/José Fonseca2014-01-17179-335/+335
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the old copyright name is creating unnecessary confusion, hence this change. This was the sed script I used: $ cat tg2vmw.sed # Run as: # # git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed # # Rename copyrights s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g /Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./ s/TUNGSTEN GRAPHICS/VMWARE/g # Rename emails s/[email protected]/[email protected]/ s/[email protected]/[email protected]/g s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/ s/jrfonseca\[email protected]/[email protected]/g s/keithw\[email protected]/[email protected]/g s/[email protected]/[email protected]/g s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/ s/[email protected]/[email protected]/ # Remove dead links s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g # C string src/gallium/state_trackers/vega/api_misc.c s/"Tungsten Graphics, Inc"/"VMware, Inc"/ Reviewed-by: Brian Paul <[email protected]>
* mesa: Eliminate parameters to dd_function_table::ScissorIan Romanick2014-01-157-28/+29
| | | | | | | | The i830 and i915 drivers used them, but they didn't really need to. They will just be annoying in future patches. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Eliminate parameters to dd_function_table::DepthRangeIan Romanick2014-01-155-9/+5
| | | | | | | No driver uses them. They will just be annoying in future patches. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Eliminate parameters to dd_function_table::ViewportIan Romanick2014-01-157-46/+8
| | | | | | | No driver uses them. They will just be annoying in future patches. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: Remove dead codeIan Romanick2014-01-151-9/+0
| | | | | | | | | A future patch will rename some of the fields of gl_viewport_attrib, and I don't want to update dead code that I can't test. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: Dave Airlie <[email protected]>
* i915: Remove spurious calls to DepthRangeIan Romanick2014-01-152-9/+2
| | | | | | | | | For both i830 and i915, the driver DepthRange function just calls intelCalcViewport. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: Eric Anholt <[email protected]>
* nouveau: add framebuffer validation callbackIlia Mirkin2014-01-152-0/+52
| | | | | | | | | | Fixes assertions when trying to attach textures to fbs with formats not supported by the render engines. See https://bugs.freedesktop.org/show_bug.cgi?id=73459 Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965: Emit 3DSTATE_VF on Broadwell too.Kenneth Graunke2014-01-141-1/+1
| | | | | | | It's not just for Haswell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Disable workaround flush for push constants on Broadwell.Kenneth Graunke2014-01-141-1/+1
| | | | | | | | If it wasn't necessary for Haswell, it's likely not to be necessary for Broadwell either. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Enable native ETC texture support on Broadwell.Kenneth Graunke2014-01-141-1/+1
| | | | | | | Broadwell, like Baytrail, has native ETC texture support. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* glsl: Convert piles of foreach_iter to the newer foreach_list macro.Kenneth Graunke2014-01-131-4/+4
| | | | | | | | | | | | | foreach_iter and exec_list_iterators have been deprecated for some time now; we just hadn't ever bothered to convert code to the newer foreach_list and foreach_list_safe macros. In these cases, we aren't editing the list, so we can use foreach_list rather than foreach_list_safe. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Ensure that all necessary state is re-emitted if we run out of aperture.Paul Berry2014-01-133-0/+21
| | | | | | | | | | | | | | | | | | | | | Prior to this patch, if we ran out of aperture space during brw_try_draw_prims(), we would rewind the batch buffer pointer (potentially throwing some state that may have been emitted by brw_upload_state()), flush the batch, and then try again. However, we wouldn't reset the dirty bits to the state they had before the call to brw_upload_state(). As a result, when we tried again, there was a danger that we wouldn't re-emit all the necessary state. (Note: prior to the introduction of hardware contexts, this wasn't a problem because flushing the batch forced all state to be re-emitted). This patch fixes the problem by leaving the dirty bits set at the end of brw_upload_state(); we only clear them after we have determined that we don't need to rewind the batch buffer. Cc: 10.0 9.2 <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* dri: set yInverted default to GL_TRUETapani Pälli2014-01-131-0/+1
| | | | | | | | | | | | yInverted is used by EGL_NOK_texture_from_pixmap to indicate that window system rendering is y-inverted compared to OpenGL texture representation. This extension is only known to be used with X11 window system where sane default is GL_TRUE. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73371 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Delete duplicate write_timestamp function.Kenneth Graunke2014-01-103-39/+8
| | | | | | | | | | brw_queryobj.c needs a version of write_timestamp that works on all generations for the QueryCounter() driver hook. So there's no point in duplicating it in gen6_queryobj.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix clears of layered framebuffers with mismatched layer counts.Paul Berry2014-01-106-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, Mesa enforced the following rule (from ARB_geometry_shader4's list of criteria for framebuffer completeness): * If any framebuffer attachment is layered, all attachments must have the same layer count. For three-dimensional textures, the layer count is the depth of the attached volume. For cube map textures, the layer count is always six. For one- and two-dimensional array textures, the layer count is simply the number of layers in the array texture. { FRAMEBUFFER_INCOMPLETE_LAYER_COUNT_ARB } However, when ARB_geometry_shader4 was adopted into GL 3.2, this rule was dropped; GL 3.2 permits different attachments to have different layer counts. This patch brings Mesa in line with GL 3.2. In order to ensure that layered clears properly clear all layers, we now have to keep track of the maximum number of layers in a layered framebuffer. Fixes the following piglit tests in spec/!OpenGL 3.2/layered-rendering: - clear-color-all-types 1d_array mipmapped - clear-color-all-types 1d_array single_level - clear-color-mismatched-layer-count - framebuffer-layer-count-mismatch Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/gen6/blorp: Remove redundant HiZ workaroundChad Versace2014-01-091-14/+0
| | | | | | | | | | | | | | | Commit 1a92881 added extra flushes to fix a HiZ hang in WebGL Google Maps. With the extra flushes emitted by the previous two patches, the flushes added by 1a92881 are redundant. Tested with the same criteria as in 1a92881: by zooming in and out continuously for 2 hours on Sandybridge Chrome OS (codename Stumpy) without a hang. CC: Kenneth Graunke <[email protected]> CC: Stéphane Marchesin <[email protected]> Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/gen6/blorp: Set need_workaround_flush at top of blorpChad Versace2014-01-091-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unconditionally set brw->need_workaround_flush at the top of gen6 blorp state emission. The art of emitting workaround flushes on Sandybridge is mysterious and not fully understood. Ken and I believe that intel_emit_post_sync_nonzero_flush() may be required when switching from regular drawing to blorp. This is an extra safety measure to prevent undiscovered difficult-to-diagnose gpu hangs. I verified that on ChromeOS, pre-patch, need_workaround_flush was not set at the top of blorp, as Paul expected. To verify, I inserted the following debug code at the top of gen6_blorp_exec(), restarted the ui, and inspected the logs in /var/log/ui. The abort gets triggered so early that the browser never appears on the display. static void gen6_blorp_exec(...) { if (!brw->need_workaround_flush) { fprintf(stderr, "chadv: %s:%d\n", __FILE__, __LINE__); abort(); } ... } CC: Kenneth Graunke <[email protected]> CC: Stéphane Marchesin <[email protected]> Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965/gen6/blorp: Set need_workaround_flush immediately after primitiveChad Versace2014-01-092-1/+3
| | | | | | | | | | | | | | | | | | | | This patch makes the workaround code in gen6 blorp follow the pattern established in the regular draw path. It shouldn't result in any behavioral change. On gen6, there are two places where we emit 3D_CMD_PRIM: brw_emit_prim() and gen6_blorp_emit_primitive(). brw_emit_prim() sets need_workaround_flush immediately after emitting the primitive, but blorp does not. Blorp sets need_workaround_flush at the bottom of brw_blorp_exec(). This patch moves the need_workaround_flush from brw_blorp_exec() to gen6_blorp_emit_primitive(). There is no need to set need_workaround_flush in gen7_blorp_emit_primitive() because the workaround applies only to gen6. Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* mesa: replace ctx->Const.{Vertex,Fragment,Geomtery}Program with an array.Paul Berry2014-01-0910-88/+88
| | | | | | | | | | | | | | | | | | | | These are replaced with ctx->Const.Program[MESA_SHADER_{VERTEX,FRAGMENT,GEOMETRY}]. In patches to follow, this will allow us to replace a lot of ad-hoc logic with a variable index into the array. With the exception of the changes to mtypes.h, this patch was generated entirely by the command: find src -type f '(' -iname '*.c' -o -iname '*.cpp' -o -iname '*.py' \ -o -iname '*.y' ')' -print0 | xargs -0 sed -i \ -e 's/Const\.VertexProgram/Const.Program[MESA_SHADER_VERTEX]/g' \ -e 's/Const\.GeometryProgram/Const.Program[MESA_SHADER_GEOMETRY]/g' \ -e 's/Const\.FragmentProgram/Const.Program[MESA_SHADER_FRAGMENT]/g' Suggested-by: Brian Paul <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't do the temporary-and-blit-copy for INVALIDATE_RANGE maps.Eric Anholt2014-01-091-1/+2
| | | | | | | | | | | | | | | | We definitely want to fall through to the unsynchronized map case, instead of wasting bandwidth on a copy. Prevents a -43.2407% +/- 1.06113% (n=49) performance regression on aa10perf when teaching glamor to provide the GL_INVALIDATE_RANGE_BIT information. This is a performance fix, which I usually wouldn't cherry-pick to stable. But this was really was just a bug in the code, its presence would discourage developers from giving us the best information they can, and I think we've got fairly high confidence in the unsynchronized map path already. Cc: 10.0 9.2 <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix handling of MESA_pack_invert in blit (PBO) readpixels.Eric Anholt2014-01-091-1/+3
| | | | | | | | | | Fixes piglit GL_MESA_pack_invert/readpixels and GPU hangs with glamor and cairo-gl. Cc: 10.0 9.2 <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Fix incorrect bounds tracking for blit readpixels's GPU access.Eric Anholt2014-01-091-2/+1
| | | | | | | | | | | While incorrect, it probably wouldn't affect anyone ever: You'd have to do an appropriately-formatted readpixels into a PBO, then overwrite the tail end of the updated area of the PBO with glBufferSubData(), and you wouldn't get appropriate synchronization. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Use SET_FIELD to safety check our x/y offsets in blits.Eric Anholt2014-01-092-7/+14
| | | | | | | | | | | | | | The earlier assert made sure that our math didn't exceed our bounds, but this makes sure that we don't overflow from the high bits X into the low bits of Y. We've already put checks in intel_miptree_blit(), but I've wanted to expand the type in our protoype from short to uint32_t, and we could get in trouble with intel_emit_linear_blit() if we did. v2: Add Ken's comment about the funny language extension used. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> (v1) Reviewed-by: Anuj Phogat <[email protected]> (v1)
* i965: Add an assert for when SET_FIELD's value exceeds the field size.Eric Anholt2014-01-091-1/+7
| | | | | | | | | This was one of the things we always wanted to do to this, to make it more useful than just (value << FIELD_MASK). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Add a safety check for emitting blits.Eric Anholt2014-01-091-0/+4
| | | | | | | | | | | | With all of the flipping and pitch twiddling and miptree layout involved in our blits, there are lots of ways for us to scribble outside of a buffer. Put in a check that we're not about to do so. This catches a bug that glamor was running into. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Don't call the blitter on addresses it can't handle.Eric Anholt2014-01-092-3/+40
| | | | | | | | | Noticed by tex3d-maxsize on my next commit to check that our addresses don't overflow. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: fold offset into coord for textureOffset(gsampler2DRect)Chris Forbes2014-01-091-1/+1
| | | | | | | | | | | | | | | | | | | | | The hardware is broken with nonzero texel offsets and unnormalized coordinates; instead of doing correct offsetting, we get garbage. This just extends the existing workaround for ir_txf and ir_tg4+gsampler2DRect to also consider ir_tex+gsampler2DRect. Fixes broken rendering in 'tesseract' when 'mesa_texrectoffset_bug' is not enabled; also fixes the new piglit test 'tests/spec/glsl-1.30/execution/fs-textureOffset-Rect'. Has been broken ~forever; suggesting including this in only 10.0 because the lowering pass doesn't exist in 9.2 or earlier so would require quite a different patch. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: Lee Salzman <[email protected]> Cc: "10.0" <[email protected]>
* glsl: Make more use of gl_shader_stage enum in ir_set_program_inouts.cpp.Paul Berry2014-01-081-1/+1
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
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