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* i965: Fix PBO cache coherency issue after _mesa_meta_pbo_GetTexSubImage().Francisco Jerez2015-05-132-2/+31
| | | | | | | | | | | | | | This problem can easily be reproduced with a number of ARB_shader_image_load_store piglit tests, which use a buffer object as PBO for a pixel transfer operation and later on bind the same buffer to the pipeline as shader image -- The problem is not exclusive to images though, and is likely to affect other kinds of buffer objects that can be bound to the 3D pipeline, including vertex, index, uniform, atomic counter buffers, etc. CC: 10.5 <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: set execution size to 8 with simd8 ddy instructionTapani Pälli2015-05-131-0/+1
| | | | | | | | | | | Commit dd5c825 changed the way how execution size for instructions get set. Previously it was based on destination register width, now it is set explicitly when emitting instructions. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90258
* i965/cs: drop explicit initialisers in C++ fileDave Airlie2015-05-131-4/+6
| | | | | | | | gcc 4.4.7 really doesn't like them, and they aren't standard C++, they seem to be a gcc extension. Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/fs: Have component() set the register stride to zero.Francisco Jerez2015-05-121-0/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix offset() for registers with zero stride.Francisco Jerez2015-05-121-2/+3
| | | | | | | stride == 0 implies that the register has one channel per vector component. Reviewed-by: Matt Turner <[email protected]>
* i965: Don't forget the force_sechalf flag in lower_load_payload().Francisco Jerez2015-05-121-0/+1
| | | | | | | Regression from commit 41868bb6824c6106a55c8442006c1e2215abf567. Fixes a bunch of ARB_shader_image_load_store tests. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Document brw_mask_reg().Francisco Jerez2015-05-121-1/+5
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Use predicate enable bit for conditional rendering w/o stallingNeil Roberts2015-05-129-12/+240
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously whenever a primitive is drawn the driver would call _mesa_check_conditional_render which blocks waiting for the result of the query to determine whether to render. On Gen7+ there is a bit in the 3DPRIMITIVE command which can be used to disable the primitive based on the value of a state bit. This state bit can be set based on whether two registers have different values using the MI_PREDICATE command. We can load these two registers with the pixel count values stored in the query begin and end to implement conditional rendering without stalling. Unfortunately these two source registers were not in the whitelist of available registers in the kernel driver until v3.19. This patch uses the command parser version from intel_screen to detect whether to attempt to set the predicate data registers. The predicate enable bit is currently only used for drawing 3D primitives. For blits, clears, bitmaps, copypixels and drawpixels it still causes a stall. For most of these it would probably just work to call the new brw_check_conditional_render function instead of _mesa_check_conditional_render because they already work in terms of rendering primitives. However it's a bit trickier for blits because it can use the BLT ring or the blorp codepath. I think these operations are less useful for conditional rendering than rendering primitives so it might be best to leave it for a later patch. v2: Use the command parser version to detect whether we can write to the predicate data registers instead of trying to execute a register load command. v3: Simple rebase v4: Changes suggested by Kenneth Graunke: Split the load_64bit_register function out to a separate patch so it can be a shared public function. Avoid calling _mesa_check_conditional_render if we've already determined that there's no query object. Some styling fixes. Reviewed-by: Kenneth Graunke <[email protected]>
* i956: Add a function to load a 64-bit register from a bufferNeil Roberts2015-05-122-14/+46
| | | | | | | | | | | | Adds brw_load_register_mem64 which is similar to brw_load_register_mem except that it queues two GEN7_MI_LOAD_REGISTER_MEM commands in order to load both halves of a 64-bit register. The function is implemented by splitting the 32-bit version into an internal helper function which takes a size. This will later be used to set the 64-bit predicate source registers. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Store the command parser version number in intel_screenNeil Roberts2015-05-122-1/+14
| | | | | | | | | In order to detect whether the predicate source registers can be used in a later patch we will need to know the version number for the command parser. This patch just adds a member to intel_screen and does an ioctl to get the version. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add missing initializer in fs_visitor().Matt Turner2015-05-111-1/+1
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* egl/swrast: Enable config extension for swrastAxel Davy2015-05-111-0/+1
| | | | | | | | Enables to use dri config for swrast, like vblank_mode. Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Axel Davy <[email protected]>
* i965/fs: Disable opt_sampler_eot for textureGatherNeil Roberts2015-05-111-0/+10
| | | | | | | | | | | | | The opt_sampler_eot optimisation seems to break when the last instruction is SHADER_OPCODE_TG4. A bunch of Piglit tests end up doing this so it causes a lot of regressions. I can't find any documentation or known workarounds to indicate that this is expected behaviour, but considering that this is probably a pretty unlikely situation in a real use case we might as well disable it in order to avoid the regressions. In total this fixes 451 tests. Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* nir: Delete all traces of nir_op_flogIan Romanick2015-05-081-3/+0
| | | | | | | | Nothing produces it, and nothing can consume it. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* nir: Delete all traces of nir_op_fexpIan Romanick2015-05-081-1/+0
| | | | | | | | Nothing produces it, and nothing can consume it. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965/fs: Improve a comment about stripping trailing zeroesNeil Roberts2015-05-081-3/+6
| | | | | | Originally I wrote that removing the first parameter doesn't work but I didn't know why. I now found a mention of this in the PRM so it's probably worthing adding it to the comment.
* i965/skl: In opt_sampler_eot always set destination register to nullNeil Roberts2015-05-081-1/+1
| | | | | | | | | | | | | opt_sampler_eot enables a direct write to framebuffer from a sample. In order to do this the sample message needs to have a message header so if there wasn't one already then the function adds one. In addition the function sets the destination register to null because it's no longer used. However it was only doing this in cases where it was adding a message header. This patch just moves setting the destination so that it happens even if there's a messge header. In practice this doesn't seem to make any difference but it's a bit cleaner. Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Set the header_size on LOAD_PAYLOAD in opt_sampler_eotNeil Roberts2015-05-081-0/+1
| | | | | | | | | | | Commit 94ee908448 added a header size parameter to the function to create the LOAD_PAYLOAD instruction. However this broke opt_sampler_eot which manually constructs the instruction and so wasn't setting the header_size. This ends up making the parameters for the send message all have the wrong location and it all falls apart. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/wm/gen6: Add option for disabling statistics collectionTopi Pohjolainen2015-05-072-4/+13
| | | | | | | | Normally this is always needed but for internal blits and clears we need to be able to disable it. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/wm/gen6: Refactor state setupTopi Pohjolainen2015-05-072-45/+77
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Remove unused variablesAnuj Phogat2015-05-071-2/+0
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Change the order of conditions tested in ifAnuj Phogat2015-05-071-3/+4
| | | | | | | | Reduces the number of conditions tested in if to one in case of non-integer formats. Makes no functional changes. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/sync: Implement DRI2_Fence extensionChad Versace2015-05-073-39/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables EGL_KHR_fence_sync and EGL_KHR_wait_sync. Below is the difference in piglit results, before and after this patch. No regressions and several tests improve from 'skip' to 'pass'. Out of EGL_KHR_fence_sync tests, two of the multithreaded tests skip; all other tests pass. cmdline: piglit run -p gbm -t sync tests/quick.py mesa: master@1ac7db0 piglit: 4069bec hw: Ivybridge | before after ------+------------- pass | 32 46 fail | 0 0 crash | 0 0 skip | 35 21 total | 67 67 v2: - Set fence->signalled = true in brw_fence_has_completed() too. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync'Chad Versace2015-05-072-28/+31
| | | | | | | | | | | | | | | | | | I'm about to implement DRI2_Fenc in intel_syncobj.c. To prevent madness, we need to prefix functions for GL_ARB_sync with 'gl' and functions for DRI2_Fence with 'dri'. Otherwise, the file will become a jumble of similiarly named functions. For example: old-name: intel_client_wait_sync() new-name: intel_gl_client_wait_sync() soon-to-come: intel_dri_client_wait_sync() I wrote this renaming commit separately from the commit that implements DRI2_Fence because I wanted the latter diff to be reviewable. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i915/sync: Return early when calloc failsChad Versace2015-05-071-0/+2
| | | | | Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sync: Return NULL when calloc failsChad Versace2015-05-071-0/+2
| | | | | Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i915/sync: Don't crash when deleting sync objectChad Versace2015-05-071-1/+3
| | | | | | | | | Don't pass NULL to drm_intel_bo_unreference(). It doesn't like that. Bug found by code inspection. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sync: Don't crash when deleting sync objectChad Versace2015-05-071-1/+3
| | | | | | | | | Don't pass NULL to drm_intel_bo_unreference(). It doesn't like that. Bug found by code inspection. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Sort extension enable listsIan Romanick2015-05-061-33/+42
| | | | | | | Sort by GEN, then sort by extension name. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Allow copy propagation on ATTR file registers.Kenneth Graunke2015-05-061-1/+4
| | | | | | | | | | | | | | | | | | | | | | This especially helps with NIR because we currently emit MOVs at the top of the shader to copy from various ATTR registers to a giant VGRF array of all inputs. (This could potentially be done better, but since there's only ever one write to each register, it should be trivial to copy propagate away...) With NIR - only vertex shaders: total instructions in shared programs: 3129373 -> 2889581 (-7.66%) instructions in affected programs: 3119717 -> 2879925 (-7.69%) helped: 20833 Without NIR - only vertex shaders: total instructions in shared programs: 2745901 -> 2724483 (-0.78%) instructions in affected programs: 693426 -> 672008 (-3.09%) helped: 3516 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs_inst: Get rid of the effective_width fieldJason Ekstrand2015-05-063-37/+3
| | | | | | | | The effective_width field was an ill-concieved hack to get around issues in the LOAD_PAYLOAD instruction. Now that the LOAD_PAYLOAD instruction is far more sane, this field can die. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Rework the fs_visitor LOAD_PAYLOAD instructionJason Ekstrand2015-05-064-236/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The newly reworked instruction is far more straightforward than the original. Before, the LOAD_PAYLOAD instruction was lowered by a the complicated and broken-by-design pile of heuristics to try and guess force_writemask_all, exec_size, and a number of other factors on the sources. Instead, we use the header_size on the instruction to denote which sources are "header sources". Header sources are required to be a single physical hardware register that is copied verbatim. The registers that follow are considered the actual payload registers and have a width that correspond's to the LOAD_PAYLOAD's exec_size and are treated as being per-channel. This gives us a fairly straightforward lowering: 1) All header sources are copied directly using force_writemask_all and, since they are guaranteed to be a single register, there are no force_sechalf issues. 2) All non-header sources are copied using the exact same force_sechalf and force_writemask_all modifiers as the LOAD_PAYLOAD operation itself. 3) In order to accommodate older gens that need interleaved colors, lower_load_payload detects when the destination is a COMPR4 register and automatically interleaves the non-header sources. The lower_load_payload pass does the right thing here regardless of whether or not the hardware actually supports COMPR4. This patch commit itself is made up of a bunch of smaller changes squashed together. Individual change descriptions follow: i965/fs: Rework fs_visitor::LOAD_PAYLOAD We rework LOAD_PAYLOAD to verify that all of the sources that count as headers are, indeed, exactly one register and that all of the non-header sources match the destination width. We then take the exec_size for LOAD_PAYLOAD directly from the destination width. i965/fs: Make destinations of load_payload have the appropreate width i965/fs: Rework fs_visitor::lower_load_payload v2: Don't allow the saturate flag on LOAD_PAYLOAD instructions i965/fs_cse: Support the new-style LOAD_PAYLOAD i965/fs_inst::is_copy_payload: Support the new-style LOAD_PAYLOAD i965/fs: Simplify setup_color_payload Previously, setup_color_payload was a a big helper function that did a lot of gen-specific special casing for setting up the color sources of the LOAD_PAYLOAD instruction. Now that lower_load_payload is much more sane, most of that complexity isn't needed anymore. Instead, we can do a simple fixup pass for color clamps and then just stash sources directly in the LOAD_PAYLOAD. We can trust lower_load_payload to do the right thing with respect to COMPR4. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make LOAD_PAYLOAD take a header sizeJason Ekstrand2015-05-064-12/+20
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make emit_single_fb_write take an explicit exec_sizeJason Ekstrand2015-05-062-8/+10
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs_inst: Add an is_copy_payload helperJason Ekstrand2015-05-064-35/+25
| | | | | | | | | | This commit adds a new is_copy_payload helper to fs_inst that takes the place of the similarly named functions in cse and register coalesce. The two is_copy_payload functions in CSE and register coalesce were subtly different and potentially subtly broken. The new version unifies the two and should be more correct. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Change header_present to header_size in backend_instructionJason Ekstrand2015-05-069-52/+56
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs_cse: Factor out code to create copy instructionsJason Ekstrand2015-05-061-37/+38
| | | | | | | | v2: Get rid of the block parameter and make src a const reference Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Make half(fs_reg, unsigned) handle register files more explicitlyJason Ekstrand2015-05-061-5/+16
| | | | | | | | | Previously, we had a special case for uniforms and immediates and then a bunch of asserts for various other pessimal things. This commit changes it so that it explicitly does something on each register file. Some of them are disallowed and others are treated properly. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix passing an immediate to half().Francisco Jerez2015-05-061-2/+2
| | | | | | | Immediates are generally uniform, they yield the same value to both halves of any instruction. Reviewed-by: Matt Turner <[email protected]>
* swrast: Build fix for darwinJeremy Huddleston Sequoia2015-05-061-0/+16
| | | | | | | | | | | Fixes regression from commit 64b1dc44495890cbc2c7c5509cb830264020998c Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90147 Signed-off-by: Jeremy Huddleston Sequoia <[email protected]> Reviewed-by: Brian Paul <[email protected]> CC: Emil Velikov <[email protected]> CC: [email protected] CC: [email protected]
* i965/gen6: Enable ARB_viewport_array and AMD_vertex_shader_viewport_indexChris Forbes2015-05-061-8/+8
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Upload all the SF viewportsChris Forbes2015-05-062-12/+19
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Upload all the clip viewportsChris Forbes2015-05-061-19/+21
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: setup limits for ARB_viewport_arrayChris Forbes2015-05-062-3/+3
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN7Marius Predut2015-05-051-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | On SNB and IVB hw, for 1 pixel line thickness or less, the general anti-aliasing algorithm give up - garbage line is generated. Setting a Line Width of 0.0 specifies the rasterization of the “thinnest” (one-pixel-wide), non-antialiased lines. Lines rendered with zero Line Width are rasterized using Grid Intersection Quantization rules as specified by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization. v2: Daniel Stone: Fix = used instead of == in an if-statement. v3: Ian Romanick: Use "._Enabled" flag insteed ".Enabled". Add code comments. re-word wrap the commit message. Add a complete bugzillia list. Improve the hardcoded values to produce better results. v4: Matt Turner: typo fixes and adjust <= 1.49 to become < 1.5 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006 Acked-by: Chris Forbes <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965: Fix missing type in local variable declaration.Kenneth Graunke2015-05-051-1/+1
| | | | | | | | | Trivial. Fixes the following compiler warning (from GCC 5.1.0): brw_context.c:629:10: warning: type defaults to ‘int’ in declaration of ‘simd_size’ [-Wimplicit-int] Signed-off-by: Kenneth Graunke <[email protected]>
* i965/vec4: Use same type for immediate, for compaction.Matt Turner2015-05-051-1/+1
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* i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN6Marius Predut2015-05-051-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | On SNB and IVB hw, for 1 pixel line thickness or less, the general anti-aliasing algorithm give up - garbage line is generated. Setting a Line Width of 0.0 specifies the rasterization of the “thinnest” (one-pixel-wide), non-antialiased lines. Lines rendered with zero Line Width are rasterized using Grid Intersection Quantization rules as specified by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization. v2: Daniel Stone: Fix = used instead of == in an if-statement. v3: Ian Romanick: Use "._Enabled" flag insteed ".Enabled". Add code comments. re-word wrap the commit message. Add a complete bugzillia list. Improve the hardcoded values to produce better results. v4: Matt Turner: typo fixes and adjust <= 1.49 to become < 1.5 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006 Acked-by: Chris Forbes <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965: Remove end-of-thread SEND alignment code.Matt Turner2015-05-051-12/+3
| | | | | | | This was present in Eric's initial implementation of the compaction code for Sandybridge (commit 077d01b6). There is no documentation saying this is necessary, and removing it causes no regressions in piglit on any platform.
* i965: Add XRGB8888 format to intel_screen_make_configsBoyan Ding2015-05-051-1/+2
| | | | | | | | | | | | | | Some application, such as drm backend of weston, uses XRGB8888 config as default. i965 doesn't provide this format, but before commit 65c8965d, the drm platform of EGL takes ARGB8888 as XRGB8888. Now that commit 65c8965d makes EGL recognize format correctly so weston won't start because it can't find XRGB8888. Add XRGB8888 format to i965 just as other drivers do. Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89689 Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
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