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path: root/src/mesa/drivers
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* i965: Fix PBO cache coherency issue after _mesa_meta_pbo_GetTexSubImage().Francisco Jerez2015-05-132-2/+31
* i965/fs: set execution size to 8 with simd8 ddy instructionTapani Pälli2015-05-131-0/+1
* i965/cs: drop explicit initialisers in C++ fileDave Airlie2015-05-131-4/+6
* i965/fs: Have component() set the register stride to zero.Francisco Jerez2015-05-121-0/+1
* i965/fs: Fix offset() for registers with zero stride.Francisco Jerez2015-05-121-2/+3
* i965: Don't forget the force_sechalf flag in lower_load_payload().Francisco Jerez2015-05-121-0/+1
* i965: Document brw_mask_reg().Francisco Jerez2015-05-121-1/+5
* i965: Use predicate enable bit for conditional rendering w/o stallingNeil Roberts2015-05-129-12/+240
* i956: Add a function to load a 64-bit register from a bufferNeil Roberts2015-05-122-14/+46
* i965: Store the command parser version number in intel_screenNeil Roberts2015-05-122-1/+14
* i965/fs: Add missing initializer in fs_visitor().Matt Turner2015-05-111-1/+1
* egl/swrast: Enable config extension for swrastAxel Davy2015-05-111-0/+1
* i965/fs: Disable opt_sampler_eot for textureGatherNeil Roberts2015-05-111-0/+10
* nir: Delete all traces of nir_op_flogIan Romanick2015-05-081-3/+0
* nir: Delete all traces of nir_op_fexpIan Romanick2015-05-081-1/+0
* i965/fs: Improve a comment about stripping trailing zeroesNeil Roberts2015-05-081-3/+6
* i965/skl: In opt_sampler_eot always set destination register to nullNeil Roberts2015-05-081-1/+1
* i965/fs: Set the header_size on LOAD_PAYLOAD in opt_sampler_eotNeil Roberts2015-05-081-0/+1
* i965/wm/gen6: Add option for disabling statistics collectionTopi Pohjolainen2015-05-072-4/+13
* i965/wm/gen6: Refactor state setupTopi Pohjolainen2015-05-072-45/+77
* i965: Remove unused variablesAnuj Phogat2015-05-071-2/+0
* i965: Change the order of conditions tested in ifAnuj Phogat2015-05-071-3/+4
* i965/sync: Implement DRI2_Fence extensionChad Versace2015-05-073-39/+158
* i965/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync'Chad Versace2015-05-072-28/+31
* i915/sync: Return early when calloc failsChad Versace2015-05-071-0/+2
* i965/sync: Return NULL when calloc failsChad Versace2015-05-071-0/+2
* i915/sync: Don't crash when deleting sync objectChad Versace2015-05-071-1/+3
* i965/sync: Don't crash when deleting sync objectChad Versace2015-05-071-1/+3
* i965: Sort extension enable listsIan Romanick2015-05-061-33/+42
* i965/fs: Allow copy propagation on ATTR file registers.Kenneth Graunke2015-05-061-1/+4
* i965/fs_inst: Get rid of the effective_width fieldJason Ekstrand2015-05-063-37/+3
* i965/fs: Rework the fs_visitor LOAD_PAYLOAD instructionJason Ekstrand2015-05-064-236/+179
* i965/fs: Make LOAD_PAYLOAD take a header sizeJason Ekstrand2015-05-064-12/+20
* i965/fs: Make emit_single_fb_write take an explicit exec_sizeJason Ekstrand2015-05-062-8/+10
* i965/fs_inst: Add an is_copy_payload helperJason Ekstrand2015-05-064-35/+25
* i965: Change header_present to header_size in backend_instructionJason Ekstrand2015-05-069-52/+56
* i965/fs_cse: Factor out code to create copy instructionsJason Ekstrand2015-05-061-37/+38
* i965/fs: Make half(fs_reg, unsigned) handle register files more explicitlyJason Ekstrand2015-05-061-5/+16
* i965/fs: Fix passing an immediate to half().Francisco Jerez2015-05-061-2/+2
* swrast: Build fix for darwinJeremy Huddleston Sequoia2015-05-061-0/+16
* i965/gen6: Enable ARB_viewport_array and AMD_vertex_shader_viewport_indexChris Forbes2015-05-061-8/+8
* i965/gen6: Upload all the SF viewportsChris Forbes2015-05-062-12/+19
* i965/gen6: Upload all the clip viewportsChris Forbes2015-05-061-19/+21
* i965/gen6: setup limits for ARB_viewport_arrayChris Forbes2015-05-062-3/+3
* i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN7Marius Predut2015-05-051-3/+18
* i965: Fix missing type in local variable declaration.Kenneth Graunke2015-05-051-1/+1
* i965/vec4: Use same type for immediate, for compaction.Matt Turner2015-05-051-1/+1
* i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN6Marius Predut2015-05-051-3/+19
* i965: Remove end-of-thread SEND alignment code.Matt Turner2015-05-051-12/+3
* i965: Add XRGB8888 format to intel_screen_make_configsBoyan Ding2015-05-051-1/+2