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* intel: Fix miptree height alignment for compressed NPOT textures.Eric Anholt2011-06-141-4/+2
* intel: Drop dead preinitialization of align_w, align_h.Eric Anholt2011-06-141-1/+1
* intel: Drop the cpp argument to intel_miptree_create().Eric Anholt2011-06-145-22/+5
* intel: Calculate compress_byte in intel_miptree_create.Eric Anholt2011-06-145-26/+18
* intel: Use the gl_format to get the base_format for miptree create.Eric Anholt2011-06-145-5/+1
* intel: Drop the internal_format field of the mipmap tree.Eric Anholt2011-06-145-15/+4
* intel: Make the intel_miptree_match_image format check more specific.Eric Anholt2011-06-142-12/+3
* i915: Drop dead argument to translate_texture_format().Eric Anholt2011-06-142-6/+3
* intel: Add block alignment for RGTC textures.Eric Anholt2011-06-144-32/+18
* intel: Add the MESA_FORMAT as a field of the miptree.Eric Anholt2011-06-145-4/+14
* intel: Fix 2x2 and 1x1 compressed teximages from _mesa_generate_mipmap()Eric Anholt2011-06-141-5/+12
* meta: Fix glCopyTexImage(GL_LUMINANCE) from non-GL_LUMINANCE source.Eric Anholt2011-06-131-0/+14
* intel: Fix mipmap and format handling of blit glCopyPixels().Eric Anholt2011-06-131-45/+53
* intel: Do the drawable x/y offset in intel_renderbuffer_map() for spans.Eric Anholt2011-06-131-64/+27
* intel: Use rb->Data and rb->RowStride to handle spans Y flipping.Eric Anholt2011-06-131-7/+4
* intel: Clean up intel_render_texture with a rename and a helper function.Eric Anholt2011-06-131-10/+6
* intel: Move the draw_x/draw_y to the renderbuffer where it belongs.Eric Anholt2011-06-1312-80/+97
* dri: include swrast.h, not s_texrender.hBrian Paul2011-06-132-2/+2
* mesa: move texrender.c to swrastBrian Paul2011-06-133-11/+10
* i965: Add support for GL_FIXED vertex attributes.Eric Anholt2011-06-104-1/+41
* Fix format not a string literal error with -Werror=format-securityEugeni Dodonov2011-06-101-1/+1
* i965/brw: Fix emit_depthbuffer() when packed depth/stencil texture is attachedChad Versace2011-06-101-11/+5
* i965/gen6: Add support for gl_PointCoord.Eric Anholt2011-06-091-0/+3
* i965/gen6: Fix point sprite texture coordinate overrides.Eric Anholt2011-06-091-7/+7
* i965/gen6: Refactor SF setup a bit to handle overrides in one place.Eric Anholt2011-06-091-19/+24
* mesa: get rid of homegrown logbase2 implementation in driversRoland Scheidegger2011-06-092-28/+2
* i965/gen7: Call gen7_create_constant_surface instead of brw_[...].Kenneth Graunke2011-06-083-3/+15
* i965/gen7: Enable SIMD16 fragment shader dispatch.Kenneth Graunke2011-06-081-2/+6
* i965/gen7: Don't emit 3DSTATE_GS_SVB_INDEX on Ivybridge.Kenneth Graunke2011-06-081-7/+9
* i965/gen7: Program stencil buffers on Ivybridge.Kenneth Graunke2011-06-081-19/+42
* i965/gen7: Add a prepare_depthbuffer function.Kenneth Graunke2011-06-081-0/+15
* i965/gen7: gen7_emit_depthbuffer needs the _NEW_DEPTH dirty bit.Kenneth Graunke2011-06-081-1/+2
* i965/gen7: Remove stencil renderbuffer from gen7_depth_format.Kenneth Graunke2011-06-081-3/+0
* intel: Request DRI2 buffers for separate stencil and hizChad Versace2011-06-083-14/+444
* intel: Add assertions to intelCreateBuffer()Chad Versace2011-06-081-3/+12
* intel: Refactor intel_update_renderbuffers()Chad Versace2011-06-081-111/+212
* intel: Add function intel_renderbuffer_set_hiz_region()Chad Versace2011-06-082-0/+17
* intel/intel_context.c: Remove unused functionsChad Versace2011-06-081-48/+0
* intel: Add flags to intel_screen for hiz and separate stencilChad Versace2011-06-083-7/+73
* intel: Define enum intel_dri2_has_hizChad Versace2011-06-081-0/+56
* intel: Define span functions for S8 renderbuffersChad Versace2011-06-081-0/+64
* i965/brw: Emit state for hiz and separate stencil buffersChad Versace2011-06-082-9/+107
* osmesa: Fix missing symbols when GLX_INDIRECT_RENDERING is defined.Jeremy Huddleston2011-06-071-0/+28
* mga: enable GL_ARB_vertex_array_object extensionNicolas Kaiser2011-06-071-0/+2
* intel: Update intel-decode.c from intel-gpu-tools.Eric Anholt2011-06-072-88/+785
* intel: Implement glFinish() correctly by waiting on all previous rendering.Eric Anholt2011-06-073-16/+13
* radeon: Use pciid list to generate PCI_CHIP_<FAMILY>_<ID> definesBenjamin Franzke2011-06-071-491/+9
* i965: Fix flipped GT1 vs GT2 URB VS entry count limits.Eric Anholt2011-06-071-2/+2
* i965: Update SURFACE_STATE dumping for Ivybridge.Kenneth Graunke2011-06-061-3/+43
* i965: Update SAMPLER_STATE dumping for Ivybridge.Kenneth Graunke2011-06-061-1/+53
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