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* i965: Update old comment about state cache sizing.Eric Anholt2010-06-111-2/+2
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* i965: Move no_batch_wrap assertion out across the area we're trying to verify.Eric Anholt2010-06-111-5/+3
| | | | | It's more likely that we wrap badly in state setup than in the little primitive packet.
* i965: remove UseProgram driver callbackBrian Paul2010-06-101-10/+0
| | | | It just duplicated the default/core Mesa behaviour.
* intel: Remove unnecessary header.Vinson Lee2010-06-101-1/+0
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* i965: Add support for GL_ALPHA framebuffer objects.Eric Anholt2010-06-106-14/+85
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* intel: Use the blitter to upload TexSubImage data to busy textures.Eric Anholt2010-06-091-10/+67
| | | | | | | | | | | | | | This avoids many pipeline stalls in cairo-gl. [ # ] backend test min(s) median(s) stddev. count Before: [ 0] gl firefox-talos-gfx 36.799 36.851 2.34% 3/3 [ 0] gl firefox-talos-svg 33.429 35.360 3.46% 3/3 After: [ 0] gl firefox-talos-gfx 35.895 36.250 0.48% 3/3 [ 0] gl firefox-talos-svg 26.669 29.888 5.34% 3/3 This doesn't avoid all the pipeline stalls because the kernel reports !busy for buffers on the flushing list. That should be fixed in .36.
* i965: Avoid calloc/free in the CURBE upload process.Eric Anholt2010-06-095-20/+26
| | | | | | | In exchange we end up with an extra memcpy, but that seems better than calloc/free. Each buffer is 4k maximum, and on the i965-streaming branch this allocation was showing up as the top entry in brw_validate_state profiling for cairo-gl.
* intel: Flag NEW_BUFFERS when changing draw buffers.Eric Anholt2010-06-081-0/+1
| | | | | | | There were entries to this function (most imporantly, prepare_render -> update_renderbuffers) that wouldn't have had NEW_BUFFERS set, but brw_wm_surface_state (the i965 state tracking the drawing regions) expected this to change.
* intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.Eric Anholt2010-06-089-60/+41
| | | | | The new API makes so much more sense, I'd like to forget how the old one worked.
* intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.Eric Anholt2010-06-0844-272/+277
| | | | | The slightly less mechanical change of converting the emit_reloc calls will follow.
* intel: Clean up stale comments in intel_batchbuffer.c.Eric Anholt2010-06-081-4/+1
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* intel: Remove the non-gem paths for batchbuffer upload.Eric Anholt2010-06-081-22/+4
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* intel: Update comment in intel_tex_copy from before miptree x/y rework.Eric Anholt2010-06-081-1/+1
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* r600: Make next_inst() static.Henri Verbeet2010-06-082-59/+61
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* r600: Assert output registers have a valid export index.Henri Verbeet2010-06-081-0/+4
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* r600: Process exports for all written fragment outputs.Henri Verbeet2010-06-081-26/+12
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* r600: Fill uiFP_OutputMap for all written fragment outputs.Henri Verbeet2010-06-081-16/+17
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* r300compiler: fix scons buildJoakim Sindholt2010-06-051-0/+2
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* i915: Only emit a MI_FLUSH when the drawing rectangle offset changes.Chris Wilson2010-06-052-8/+24
| | | | Signed-off-by: Chris Wilson <[email protected]>
* i915: Fix off-by-one for drawing rectangle.Chris Wilson2010-06-051-2/+2
| | | | | | | | | | | | | | | The drawing rectangle is given in *inclusive* pixel values, so the range is only [0,2047]. Hence when rendering to a 2048 wide target, such as an extended desktop, we would issue an illegal instruction zeroing the draw area. Fixes: Bug 27408: Primary and Secondary display blanks in extended desktop mode with Compiz enabled https://bugs.freedesktop.org/show_bug.cgi?id=27408 Signed-off-by: Chris Wilson <[email protected]>
* i915: Inhibit render cache flush when changing drawing rectangle offset.Chris Wilson2010-06-051-1/+1
| | | | Signed-off-by: Chris Wilson <[email protected]>
* r300/compiler: implement SIN+COS+SCS for vertex shadersMarek Olšák2010-06-053-21/+76
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* r300/compiler: implement SNE unwound for r3xx VS, natively for r5xx VSMarek Olšák2010-06-052-1/+37
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* r300/compiler: implement SEQ unwound for r3xx VS, natively for r5xx VSMarek Olšák2010-06-052-0/+36
| | | | Fixes piglit/glsl-vs-vec4-indexing-4.
* r300/compiler: implement SFL for vertex shadersMarek Olšák2010-06-051-2/+3
| | | | And sort the "case" statements alphabetically.
* i915: Don't use XRGB8888 on 830 and 845.Eric Anholt2010-06-043-2/+18
| | | | | | | | | The support for XRGB8888 appeared in the 855 and 865, and this format is reserved on 830/845. This should fix a regression from b4a6169412819cc3a027c6a118f0537911145a30 that caused hangs in etracer on 845s. Bug #26557.
* i915: Clamp minimum lod to maximum texture level too.Eric Anholt2010-06-041-1/+3
| | | | | | | Otherwise, we'd run into minlod > maxlod, and the sampler would give us the undefined we asked for. Bug #24846. Fixes OGLC texlod.c.
* intel: Fix intel_compressed_num_bytes for FXT1 after I broke it.Eric Anholt2010-06-041-1/+1
| | | | | | | | Fixes piglit fxt1-teximage since 7554b83a21bd62b20df5a7327b69f08108ac9ab6, and also OGLC tests that hit FXT1 with a million other things. Bug #28184.
* r300/compiler: print opcode names instead of numbersMarek Olšák2010-06-033-8/+8
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* dri/swrast: Remove unnecessary header.Vinson Lee2010-06-021-1/+0
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* intel: Remove a leftover DRI1/DRI2 conditionalKristian Høgsberg2010-06-021-7/+2
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* intel: Fallback to meta if we're asked to CopyTexImage2D from RGB to RGBAKristian Høgsberg2010-06-011-0/+8
| | | | | | | The pixel transfer rules state that we must set alpha to 1.0 in this case which we can't easily do with the blitter. We can do to passes: one that sets the alpha to 0xff and one that copies the RGB bits or we can just use the 3D engine. Neither approach seems worth it for this case.
* swrast: add TFP support to swrast.Dave Airlie2010-05-311-0/+69
| | | | | | | | | This adds TFP support to the swrast driver, with this I can run gnome-shell inside Xephyr slowly. I've no idea why I did it, and g-s has other rendering issues under swrast, but it might be useful to hook up llvmpipe later. I've no idea if I even want to commit it at this point. An enhanced version might just pass the pointer in the indirect rendering case and avoid the memcpy. Signed-off-by: Dave Airlie <[email protected]>
* gallium: fix TFP on galliumDave Airlie2010-05-311-0/+1
| | | | | | | | This fixes an uninitialised value use in the dri2 st when doing TFP. It uses the driContextPriv which isn't initialised at alloc time. Signed-off-by: Dave Airlie <[email protected]>
* intel: Initialize batch->reserved_space on allocationChris Wilson2010-05-311-2/+1
| | | | | | | | | | | | | | Fixes the assert (and buffer overrun): glknots: intel_batchbuffer.c:164: _intel_batchbuffer_flush: Assertion 'used >= batch->buf->size' failed. Reported in bug: Bug 28274 - xscreensaver's glknots hangs GPU (945GME/Pineview) https://bugs.freedesktop.org/show_bug.cgi?id=28274 Signed-off-by: Chris Wilson <[email protected]>
* r300: fix blits for textures of width/height greater than 2048 on r5xxMarek Olšák2010-05-291-5/+9
| | | | Yes I am fixing r300c ... who knew?
* i965: Add cache unit -> bo name mapping for more gen6 state objects.Eric Anholt2010-05-281-0/+3
| | | | This will help in bufmgr debugging and aub dumping.
* i965: fix PIPE_CONTROL command for gen6.Zou Nan hai2010-05-281-1/+10
| | | | | Signed-off-by: Zou Nan hai <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* fbdev: some hacking to get the driver to compile (untested)Brian Paul2010-05-271-1/+7
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* Enable hardware mipmap generation for radeon.Will Dyson2010-05-261-3/+8
| | | | | | | Use _mesa_meta_GenerateMipmap. It is Fast Enough(tm). Signed-off-by: Maciej Cencora <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Fix image_matches_texture_obj() MaxLevel checkWill Dyson2010-05-261-4/+7
| | | | | | | | | When generating or uploading a new (higher) mipmap level for an image, we can need to allocate a miptree for a level greater than texObj->MaxLevel. Signed-off-by: Maciej Cencora <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* Fallback to software render if there is no miptree for an imageWill Dyson2010-05-261-4/+4
| | | | | | | | This can happen when checking if a software fallback for a higher level operation (such as GenerateMipmap) is needed. Signed-off-by: Maciej Cencora <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* i965: Add support for EXT_timer_query on Ironlake.Eric Anholt2010-05-262-24/+67
| | | | | | We could potentially do this on G45 as well, though the units are different. On 965, the timestamp is tied to hclk, which would make supporting it harder.
* intel: Handle decode of PIPE_CONTROL instructions.Eric Anholt2010-05-261-0/+27
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* i965: Move Gen6 debugging emit_mi_flush into the Gen6 block.Eric Anholt2010-05-261-2/+2
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* i965: Don't PIPE_CONTROL instruction cache flush.Eric Anholt2010-05-261-1/+0
| | | | | | | | | | | | This is a workaround for Ironlake errata. The emit_mi_flush is used for a few purposes: 1) Flushing write caches for RTT (including blit to texture) 2) Pipe fencing for sync objects 3) Spamming cache flushes to track down cache flush bugs Spamming cache flushes seems less important than following the docs, and we should probably do that with a different mechanism than the one for render cache flushes.
* i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.Eric Anholt2010-05-261-0/+7
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* r300/compiler: implement SGT+SLE opcodesMarek Olšák2010-05-261-0/+20
| | | | Reported-by: Gianluca Anzolin <[email protected]>
* r300/compiler: fix dumping r5xx vertex shadersMarek Olšák2010-05-261-0/+3
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* r300/compiler: move hardware caps to the radeon_compiler base structMarek Olšák2010-05-266-18/+19
| | | | Needed for vertex shaders too.
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