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* scons: Build classic mesa gdi driver.José Fonseca2011-04-236-115/+52
| | | | | | Build as scons platform=windows mesagdi
* osmesa: Fix Mingw build.José Fonseca2011-04-231-16/+1
| | | | | | Build as scons platform=windows osmesa
* scons: Build osmesa.José Fonseca2011-04-232-0/+37
| | | | | | Just type scons osmesa
* r300/compiler: fix up error messageMarek Olšák2011-04-221-2/+2
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* i915: Gut all remaining bits of hardware fogIan Romanick2011-04-214-107/+13
| | | | | | | | | | | None of this ever gets used. Fog is always calculated by a fragment program. Even though the fixed-function fog unit is never used, state updates are still sent to the hardware. Removing those spurious state updates can't hurt performance. Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i915: i915_context::vertex_fog is always I915_FOG_NONE, so kill itIan Romanick2011-04-213-8/+1
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i915: There's always a fragment programIan Romanick2011-04-211-26/+5
| | | | | | | | | | Fragment programs are generated by core Mesa for fixed-function. Because of this, there's no reason to handle cases where there is no fragment program for fog. Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i915: Delete disabled try_pixel_fog pathsIan Romanick2011-04-211-55/+0
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* mesa: Kill gl_fragment_program::FogOption with fireIan Romanick2011-04-211-2/+0
| | | | | | | | | | | | All drivers expect this to always be GL_NONE. Don't let there be any opportunity for a bad value to leak out and infect some unsuspecting driver. If any driver for hardware that had fixed-function per-fragment fog (i915 and perhaps some r300-ish) was ever going to add support, it would have done it by now. Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i915: gl_fragment_program::FogOption is always GL_NONE so don't check itIan Romanick2011-04-212-11/+2
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i965: gl_fragment_program::FogOption is always GL_NONE so don't check itIan Romanick2011-04-211-5/+0
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i965: Remove dead vertex buffer structs.Kenneth Graunke2011-04-201-25/+0
| | | | We do this OUT_BATCH-style in brw_draw_upload.c.
* intel: Add support for ARB_color_buffer_float.Eric Anholt2011-04-209-10/+28
| | | | Reviewed-by: Brian Paul <[email protected]>
* meta: Add support for ARB_color_buffer_float to _mesa_meta_Clear().Eric Anholt2011-04-201-4/+24
| | | | | | Tested with piglit arb_color_buffer_float-clear. Reviewed-by: Brian Paul <[email protected]>
* meta: Add support for ARB_color_buffer_float to _mesa_meta_DrawPixels.Eric Anholt2011-04-201-0/+28
| | | | | | Tested with piglit arb_color_buffer_float-drawpixels. Reviewed-by: Brian Paul <[email protected]>
* intel: Add support for ARB_texture_float.Eric Anholt2011-04-206-2/+62
| | | | | | | | | | | | For 1 and 2-channel formats the hardware only supports rendering to R and RG. To do I and L render targets we just call them R and everything works out. For A, we would need to rewrite the CC to do the alpha channel's blending on color instead, and send the fragment alpha down the red channel. For LA, there doesn't seem to be any hope, because we can't do independent color/alpha blending while treating the LA surface as RG. Reviewed-by: Brian Paul <[email protected]>
* intel: Add support for blit copies of >32bpp formats.Eric Anholt2011-04-201-0/+11
| | | | | | | | | The blitter only does up 32bpp at a time, so we handle it by mangling coordinates and calling the surface 32bpp. Fixes ARB_texture_rg/fbo-generatemipmap-formats-float with ARB_texture_float. Reviewed-by: Brian Paul <[email protected]>
* r600c: add evergreen big endian supportAlex Deucher2011-04-195-9/+286
| | | | | | Based on Cedric's r6xx/r7xx patch. Signed-off-by: Alex Deucher <[email protected]>
* r600c: add big endian support for r6xx/r7xxCédric Cano2011-04-1911-50/+508
| | | | | Signed-off-by: Cedric Cano <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r200: enable some extensionsMarek Olšák2011-04-191-2/+10
| | | | | | | | Such as: - GL_ARB_half_float_pixel - GL_ARB_vertex_array_object - GL_APPLE_vertex_array_object - GL_EXT_gpu_program_parameters
* r300/compiler: Fix dataflow analysis bug with ELSE blocksTom Stellard2011-04-181-0/+7
| | | | | | | Writes within ELSE blocks were being ignored which prevented us from discovering all possible writers for some register values. Fixes piglit glsl-fs-raytrace-bug27060
* i965: Convert 3DPRIMITIVE command from struct-style to OUT_BATCH style.Kenneth Graunke2011-04-183-46/+37
| | | | | | | | | | Most of the newer portions of the code use OUT_BATCH style. I prefer this style because it offers a clear distinction between a) hardware messages/structures with a mandatory format, and b) data structures for our own internal use that we can format however we want. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Allocate the whole URB to the VS and fix calculations for Gen6.Kenneth Graunke2011-04-183-19/+25
| | | | | | | | | | | | | | | | | Since we never enable the GS on Sandybridge, there's no need to allocate it any URB space. Furthermore, the previous calculation was incorrect: it neglected to multiply by nr_vs_entries, instead comparing whether twice the size of a single VS URB entry was bigger than the entire URB space. It also neglected to take into account that vs_size is in units of 128 byte blocks, while urb_size is in bytes. Despite the above problems, the calculations resulted in an acceptable programming of the URB in most cases, at least on GT2. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Add I8 and L8 to intel_mesa_format_to_rb_datatype().Eric Anholt2011-04-181-0/+2
| | | | | | Fixes warnings in fbo-storage-formats. Reviewed-by: Brian Paul <[email protected]>
* Revert "intel: Add spans code for the ARB_texture_rg support."Eric Anholt2011-04-181-122/+0
| | | | | | | | | This reverts what remains of commit 28bab24e1698843e27d27204a1117066e7ffeabb. It was garbage, trying to use a MESA_FORMAT enum as a preprocessor token, and I don't know how I thought it was even tested. Reviewed-by: Brian Paul <[email protected]>
* intel: Use mesa core's R8, RG88, R16, RG1616 RB accessors.Eric Anholt2011-04-181-25/+4
| | | | | | | Fixes: ARB_texture_rg/fbo-alphatest-formats Reviewed-by: Brian Paul <[email protected]>
* intel: Use Mesa core's renderbuffer accessors for depth.Eric Anholt2011-04-181-33/+15
| | | | | | | | | | | Since we're using GTT mappings now (no manual detiling), there's really nothing special to accessing these buffers, other than needing the new RowStride field of gl_renderbuffer to accomodate padding. Reduces the driver size by 2.7kb, and improves glean depthStencil performance 3-10x (!) Reviewed-by: Brian Paul <[email protected]>
* intel: Use _mesa_base_tex_format for FBO texture attachments.Eric Anholt2011-04-181-1/+1
| | | | | | | | | | | | The _mesa_base_fbo_format variant doesn't handle some texture internalformats, such as "3". Fixes: fbo-blending-formats. fbo-alphatest-formats EXT_texture_sRGB/fbo-alphatest-formats Reviewed-by: Brian Paul <[email protected]>
* i965: Quit spamming gen6 DP read/write send instructions with gen5 bits.Eric Anholt2011-04-171-6/+0
| | | | | | This was copy-and-paste from originally trying to get DP read/write working reliably, and notably for other common messages (URB, sampler) we weren't doing this.
* i965/fs: Add gen6 register spilling support.Eric Anholt2011-04-175-31/+58
| | | | | | | | | | | Most of this is code movement to get the scratch space allocated in a shared location. Other than that, the only real changes are that the old oword block messages now operate on oword-aligned areas (with new messages for unaligned access, which we don't do), and that the caching control is in the SFID part of the descriptor instead of message control. Fixes glsl-fs-convolution-1.
* r300/compiler: Fix incorrect presubtract conversionTom Stellard2011-04-161-0/+24
| | | | | | | ADD instructions with constant swizzles can't be converted to presubtract operations. NOTE: This is a candidate for the 7.9 and 7.10 branches.
* Revert "r300/compiler: Don't try to convert RGB to Alpha in full instructions"Marek Olšák2011-04-151-2/+1
| | | | | | This reverts commit cd2857fae16e1352f39b37f611797e66619d3fe5. It breaks Unigine Heaven.
* mesa: finish up ARB_texture_floatMarek Olšák2011-04-152-2/+0
| | | | | | | | | | | | | | | Squashed commit of the following: Author: Marek Olšák <[email protected]> mesa: handle floating-point formats in _mesa_base_fbo_format mesa: add ARB/ATI_texture_float, remove MESAX_texture_float commit 123bb110852739dffadcc81ad80b005b1c4f586d Author: Luca Barbieri <[email protected]> Date: Wed Aug 25 01:35:42 2010 +0200 mesa: compute floatMode for FBOs and return it on RGBA_FLOAT_MODE
* i965/fs: Constant-fold immediates in src0 of SEL instructions.Eric Anholt2011-04-134-0/+16
| | | | | | | | | | | This is like what we do for add/mul, but we have to invert the predicate to choose the other source instead. This removes 5 extra moves of constants in nexuiz shaders. No statistically significant performance difference on my Sandybridge laptop (n=5). Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Constant-fold immediates in src0 of CMP instructions.Eric Anholt2011-04-133-0/+45
| | | | | | | This is like what we do with add/mul, but we also have to flip the conditional test. Reviewed-by: Ian Romanick <[email protected]>
* i965: Change assertion condition from implicit to explicitChad Versace2011-04-121-2/+1
| | | | | | | | | | | | | ... because grokking explicit assertions requires fewer neurons. In brw_misc_state.c:emit_depthbuffer, change assertion condition tiling != I915_TILING_X && tiling != I915_TILING_NONE to tiling == I915_TILING_Y Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Define BRW_DEPTHFORMAT_D24_UNORM_X8_UINTChad Versace2011-04-121-0/+1
| | | | | | | This depth format was added in Gen5. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Document brw_context.state.depth_regionChad Versace2011-04-122-1/+23
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Remove unnecessary release/reference of brw_context.state.depth_regionChad Versace2011-04-121-6/+4
| | | | | | | | Release the old depth region and reference the new one *only* if it has changed. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Add comments about URB size units and limits.Kenneth Graunke2011-04-122-4/+10
| | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Acked-by: Chris Wilson <[email protected]>
* i965: Never enable the GS on Gen6.Kenneth Graunke2011-04-121-32/+16
| | | | | | | | | | | | | Prior to Gen6, we use the GS for breaking down quads, quad-strips, and line loops. On Gen6, earlier stages already take care of this, so we never need the GS. Since this code is likely completely untested, remove it for now. We can write new code when enabling real geometry shaders. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* Revert "i965: Reinstate max-index paranoia"Chris Wilson2011-04-121-1/+1
| | | | | | | | | | | | | | | | | | This reverts commit b4cbd2b312d53a50603e2cda925711bc9def4517. It looked like a safe sanity check. It missed the issue of the start of the buffer not being at 0, but even that was not enough to explain why setting the max vertex index caused glyphs to be dropped from the game 'Achron'. Instead, the issue appears to be related to the use of the vertex bias and so we would need to re-emit the max-index every time we adjusted the bias, so re-emitting the relocations and defeating the original optimisation. Reported-and-tested-by: Thomas Jones <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35163 Signed-off-by: Chris Wilson <[email protected]>
* nouveau_vieux: fix build since sampler objects mergeDave Airlie2011-04-123-12/+12
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* r600: silence various compiler warningsBrian Paul2011-04-117-10/+19
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* Merge branch 'arb_sampler_objects'Brian Paul2011-04-1134-228/+232
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| * mesa: fixup r600 DRI driver for sampler object changesBrian Paul2011-04-114-26/+26
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| * mesa: move sampler state into new gl_sampler_object typeBrian Paul2011-04-1034-218/+222
| | | | | | | | | | | | gl_texture_object contains an instance of this type for the regular texture object sampling state. glGenSamplers() generates new instances of gl_sampler_object which can override that state with glBindSampler().
* | Revert "i965: clear global offset to zero in m0.2 for VS DP read."Zou Nan hai2011-04-121-9/+0
| | | | | | | | | | This reverts commit 66b66295d0bc856c69fdcccc22575580c7ecee16. it was already fixed by commit 9d60a7ce08a67eb8b79c60f829d090ba4a37ed7e
* | i965: Remove hint_gs_always and resulting dead codeIan Romanick2011-04-113-76/+13
| | | | | | | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* | intel: Fix ROUND_DOWN_TO macroIan Romanick2011-04-111-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the macro would (ALIGN(value - alignment - 1, alignment)). At the very least, this was missing parenthesis around "alignment - 1". As a result, if value was already aligned, it would be reduced by alignment. Condisder: x = ROUND_DOWN_TO(256, 128); This becomes: x = ALIGN(256 - 128 - 1, 128); Or: x = ALIGN(127, 128); Which becomes: x = 128; This macro is currently only used in brw_state_batch (brw_state_batch.c). It looks like the original version of this macro would just use too much space in the batch buffer. It's possible, but not at all clear to me from the code, that the original behavior is actually desired. In any case, this patch does not cause any piglit regressions on my Ironlake system. I also think that ALIGN_FLOOR would be a better name for this macro, but ROUND_DOWN_TO matches rounddown in the Linux kernel. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Keith Whitwell <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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