summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers
Commit message (Collapse)AuthorAgeFilesLines
* i965/skl: Remove early platform supportBen Widawsky2015-08-131-10/+0
| | | | | | | | | | | | | | | | We do not want bug reports from this early stepping of SKL. Few if any were ever shipped outside of Intel to early enabling partners, and none will be sold. There is a functional change here. If you're using new mesa on an old kernel/libdrm, the revid will be -1, and we'll use new SKL values instead of early ones (a hopefully irrelevant improvement IMO). v2: Remove hunk which warned before dying. Instead, default to normal SKL support (Ken) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Stop aux data compare preventing program binary re-useTopi Pohjolainen2015-08-131-32/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Items in the program cache consist of three things: key, the data representing the instructions and auxiliary data representing uniform storage. The data consisting of instructions is stored into a drm buffer object while the key and the auxiliary data reside in malloced section. Now the cache uploading is equipped with a check that iterates over existing items and seeks to find a another item using identical instruction data than the one being just uploaded. If such is found there is no need to add another section into the drm buffer object holding identical copy of the existing one. The item just being uploaded should instead simply point to the same offset in the underlying drm buffer object. Unfortunately the check for the matching instruction data is coupled with a check for matching auxiliary data also. This effectively prevents the cache from ever containing two items that could share a section in the drm buffer object. The constraint for the instruction data and auxiliary data to match is, fortunately, unnecessary strong. When items are stored into the cache they will anyway contain their own copy of the auxiliary data (even if they matched - which they in real world never will). The only thing the items would be sharing is the instruction data and hence we should only check for that to match and nothing else. No piglit regression in jenkins. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Only write program to cache when it doesn't exist yetTopi Pohjolainen2015-08-131-7/+7
| | | | | | | | | | | Current logic re-writes the same data when existing data is found. Not that this actually matters at the moment in practice, the contraint for finding matching data is too severe to ever allow data to be shared between two items in the cache. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Rename brw_upload_item_data to brw_alloc_item_dataTopi Pohjolainen2015-08-131-9/+10
| | | | | | | | | | and simplify the interface to take directly the size and to return the offset. The routine does nothing more than allocate, it doesn't upload anything. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/shader: Don't use OptimizeForAOS for NIR vec4 vertex shadersJason Ekstrand2015-08-121-1/+1
| | | | | | | | | | | | | | Shader-db results for vec4 programs using NIR on HSW: total instructions in shared programs: 1838157 -> 1828469 (-0.53%) instructions in affected programs: 275978 -> 266290 (-3.51%) helped: 2827 HURT: 244 GAINED: 0 LOST: 0 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965: Optimize brw_inst_set_bits() and brw_compact_inst_set_bits().Matt Turner2015-08-111-4/+4
| | | | | | | | | | Cuts about 2k of .text. text data bss dec hex filename 5017141 197160 27672 5241973 4ffc75 i965_dri.so before 5014981 197160 27672 5239813 4ff405 i965_dri.so after Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Optimize brw_inst_bits() and brw_compact_inst_bits().Matt Turner2015-08-111-4/+4
| | | | | | | | | | Cuts about 1k of .text. text data bss dec hex filename 5018165 197160 27672 5242997 500075 i965_dri.so before 5017141 197160 27672 5241973 4ffc75 i965_dri.so after Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Expose ARB_shader_image_load_store.Francisco Jerez2015-08-111-0/+1
| | | | | Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Clamp image array indices to the array bounds on IVB.Francisco Jerez2015-08-111-4/+21
| | | | | | | | | | | This fixes the spec@arb_shader_image_load_store@invalid index bounds piglit tests on IVB, which were causing a GPU hang and then a crash due to the invalid binding table index result of the array index calculation. Other generations seem to behave sensibly when an invalid surface is provided so it doesn't look like we need to care. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Translate image load, store and atomic NIR intrinsics.Francisco Jerez2015-08-111-0/+106
| | | | | | v2: Move array coordinate workaround into the surface builder. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Handle image uniforms in NIR programs.Francisco Jerez2015-08-112-8/+44
| | | | | | v2: Move the image_params array back to brw_stage_prog_data. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Implement logic to set up and upload an image uniform.Francisco Jerez2015-08-112-0/+32
| | | | | | v2: Move the image_params array back to brw_stage_prog_data. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Teach type_size() about the size of an image uniform.Francisco Jerez2015-08-112-0/+2
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Implement image load, store and atomic.Francisco Jerez2015-08-112-0/+264
| | | | | | | | v2: Drop VEC4 suport. v3: Rebase. v4: Move array coordinate workaround into the surface builder. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Import image format conversion primitives.Francisco Jerez2015-08-111-0/+265
| | | | | | | | | | | | | | | | | | | Define bitfield packing, unpacking and type conversion operations in terms of which the image format conversion code will be implemented. These don't directly know about image formats: The packing and unpacking functions take a 4-tuple of bit shifts and a 4-tuple of bit widths as arguments, determining the bitfield position of each component. Most of the remaining functions perform integer, fixed point normalized, and floating point type conversions, mapping between a target type with per-component bit widths given by a parameter and a matching native representation of the same type. v2: Drop VEC4 suport. v3: Rebase. v4: Fix clamping of negative floats in the unsigned case of emit_convert_to_scaled(). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Import image format metadata queries.Francisco Jerez2015-08-111-0/+148
| | | | | | | | | | | Define some utility functions to query the bitfield layout of a given image format and whether it satisfies a number of more or less hardware-specific properties. v2: Drop VEC4 suport. v3: Add SKL support. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Import code to transform image coordinates into surface coordinates.Francisco Jerez2015-08-111-0/+52
| | | | | | Accounting for the padding required for 1D arrays in certain cases. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Import image memory offset calculation code.Francisco Jerez2015-08-111-0/+169
| | | | | | | | | | | | | | | | | | | | | | Define a function to calculate the memory address of the image location given by a vector of coordinates. This is required in cases where we need to fall back to untyped surface access, which take a raw memory offset and know nothing about surface coordinates, type conversion or memory tiling and swizzling. They are still useful because typed surface reads don't support any 64 or 128-bit formats on IVB, and they don't support any 128-bit formats on HSW and BDW. The tiling algorithm is implemented based on a number of parameters which are passed in as uniforms and determine whether the surface layout is X-tiled, Y-tiled or untiled. This allows binding surfaces of different tiling layouts to the pipeline without recompiling the program. v2: Drop VEC4 suport. v3: Rebase. v4: Add plenty of comments (Jason). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Import image access validity checks.Francisco Jerez2015-08-111-0/+55
| | | | | | | | | | | | | | These utility functions check whether an image access is valid. According to the spec an invalid image access should have no effect on the image and yield well-defined results. Typically the hardware implements correct bounds and surface checking by itself, but in some cases (typed atomics on IVB and untyped messages elsewhere) we need to implement it in software to work around lacking hardware support. v2: Drop VEC4 suport. v3: Rebase. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Define implementation constants for ARB_shader_image_load_store.Francisco Jerez2015-08-111-0/+12
| | | | | | | | Reviewed-by: Paul Berry <[email protected]> v2: Drop VS support pre-Gen8, drop GS support. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7-8: Set up early depth/stencil control appropriately for image ↵Francisco Jerez2015-08-116-3/+21
| | | | | | | | | load/store. v2: Store early fragment test mode in brw_wm_prog_data instead of getting it from core mesa data structures (Ken). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7-8: Poke the 3DSTATE UAV access enable bits.Francisco Jerez2015-08-117-9/+32
| | | | | | v2: Set the PS UAV-only bit on HSW (Ken). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7: Enable fragment shader dispatch if the program has image uniforms.Francisco Jerez2015-08-111-0/+1
| | | | | | | | | | | | Shaders with image uniforms may have side effects. Make sure that fragment shader threads are dispatched if the shader has any image uniforms. v2: Use brw_stage_prog_data::nr_image_params to find out if the shader has image uniforms instead of checking core mesa data structures (Ken). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Hook up image state upload.Francisco Jerez2015-08-116-2/+146
| | | | | | | | v2: Add CS support. Move the image_params array back to brw_stage_prog_data. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965: Reserve enough parameter entries for all image uniforms used in the ↵Francisco Jerez2015-08-114-3/+7
| | | | | | | | | program. v2: Add CS support. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Define and initialize image parameter structure.Francisco Jerez2015-08-116-1/+170
| | | | | | | | | | | | | | | | This will be used to pass image meta-data to the shader when we cannot use typed surface reads and writes. All entries except surface_idx and size are otherwise unused and will get eliminated by the uniform packing pass. size will be used for bounds checking with some image formats and will be useful for ARB_shader_image_size too. surface_idx is always used. v2: Add CS support. Move the image_params array back to brw_stage_prog_data. v3: Improve documentation. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Implement surface state set-up for shader images.Francisco Jerez2015-08-113-0/+188
| | | | | | v2: Add SKL support. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix brw_memory_barrier() for SKL.Francisco Jerez2015-08-111-1/+1
| | | | | | This works as-is on SKL, only the assertion needs to be relaxed. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().Francisco Jerez2015-08-111-3/+1
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* nouveau: no need to do tnl wakeup, state updates are always hooked upIlia Mirkin2015-08-102-2/+0
| | | | | | | | | | A TNL state update now requires a DrawBuffer to be set, which it isn't early on in context creation. Since we init swtnl from context init, this caused crashes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91570 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6" <[email protected]>
* i965/fs: Make resolve_source_modifiers consistent with the vec4 versionJason Ekstrand2015-08-103-15/+16
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4_visitor: Make some function arguments const referencesJason Ekstrand2015-08-102-6/+6
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Don't do redundant RA setup on IVB+Jason Ekstrand2015-08-101-0/+9
| | | | Acked-by: Matt Turner <[email protected]>
* i965/fs: Use dispatch_width instead of reg_width in alloc_reg_setsJason Ekstrand2015-08-101-8/+8
| | | | | | reg_width is kind of an outdated concept. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4_nir: Properly handle integer multiplies on BDW+Jason Ekstrand2015-08-101-24/+28
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4_nir: Do boolean source modifier resolves on BDW+Jason Ekstrand2015-08-103-0/+29
| | | | | | | | | | On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually a boolean negate and not an integer negate. However, NIR's soruce modifiers are the integer version. We have to resolve it with a MOV prior to emitting the actual instruction. This is basically the same thing we do in the FS backend. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4-nir: Handle boolean resolvese on ILK-Jason Ekstrand2015-08-101-0/+14
| | | | | | | The analysis code was already there and running, we just weren't doing anything with the result of it yet. Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Don't mark bany or ball instructions for resolveJason Ekstrand2015-08-101-0/+23
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Use nir_op_info.output_type for determining when to resolveJason Ekstrand2015-08-101-25/+15
| | | | | | | | | | | Previously, we were explicitly listing every instruction that needs a resolve. However, those instructions were precicely the ones that returned booleans so there's no reason why we shouldn't just have that check. Also, all of the reduction opcodes such as bany and ball were missing so it didn't properly flag stuff on vec4. If an opcode gets added in the future that returns a bool but doesn't need a resolve, we can special-case that. Reviewed-by: Matt Turner <[email protected]>
* i965/skl: (trivial) Remove invalid comment about thread countsBen Widawsky2015-08-071-1/+0
| | | | | | | | | | | This should have been a part of: commit 7eaacc1678195738fab3bb98870828611cae066d Author: Ben Widawsky <[email protected]> Date: Wed Jul 29 12:35:24 2015 -0700 i965/skl: Add production thread counts and URB size Signed-off-by: Ben Widawsky <[email protected]>
* i965: Fix HW binding tables editingChris Wilson2015-08-071-6/+9
| | | | | | | | | | | | | | | | | | | | | | Since the introduction of new gl_shader_stages in commit a2af956963b6bc4d29f37485e44c98008d2ef077 Author: Fabian Bieler <[email protected]> Date: Fri Mar 7 10:19:09 2014 +0100 mesa: add tessellation shader enums the translation table for the stage into the HW binding table edit command was broken, and so we used illegal commands. Fix the array initialisation to be impervious to changes in the gl_shader_stages enum and add the asserts that would have caught the issue earlier. Signed-off-by: Chris Wilson <[email protected]> Cc: Abdiel Janulgue <[email protected]> Cc: Jordan Justen <[email protected]> Cc: Matt Turner <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix indentation in vec4_visitor::evaluate_spill_costsIago Toral Quiroga2015-08-071-12/+12
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* i965/vec4: do not predicate scratch writes for BRW_OPCODE_SEL instructionsIago Toral Quiroga2015-08-071-1/+2
| | | | | | | | The dst is always written, in this case the predicate is only used to select the value to write, so if we are spilling the dst we always want to write whatever value we selected to scratch. Reviewed-by: Francisco Jerez <[email protected]>
* i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.Matt Turner2015-08-067-20/+20
| | | | | | | | | Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it needed to include no tiling at all, but the name MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid confusion by replacing "ALLOC" with "TILING" in the identifiers. Reviewed-by: Ben Widawsky <[email protected]>
* i965: Correct a mistake that always forced texture tiling.Matt Turner2015-08-061-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Regression since commit 3a31876600, when tiling modes were moved into layout_flags. The relevant enum values are MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5 MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6 MIPTREE_LAYOUT_ALLOC_ANY_TILED = MIPTREE_LAYOUT_ALLOC_YTILED | MIPTREE_LAYOUT_ALLOC_XTILED MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 7 so the expression (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) can never produce a value of MIPTREE_LAYOUT_ALLOC_LINEAR. The enum this replaced was enum intel_miptree_tiling_mode { INTEL_MIPTREE_TILING_ANY, INTEL_MIPTREE_TILING_Y, INTEL_MIPTREE_TILING_NONE, }; where "ANY" means "Y" or "NONE" (i.e., linear). As such, remove the unused (and worse, unhandled) MIPTREE_LAYOUT_ALLOC_XTILED and redefine MIPTREE_LAYOUT_ALLOC_ANY_TILED to mean what it did before. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91513 Reviewed-by: Ben Widawsky <[email protected]>
* i965: Request a miptree with no tiling intel_miptree_map_blit().Matt Turner2015-08-061-1/+1
| | | | | | | Regression since commit 3a31876600, when tiling modes were moved into layout_flags. Reviewed-by: Ben Widawsky <[email protected]>
* vbo: pass the stream from DrawTransformFeedbackStream to driversMarek Olšák2015-08-065-6/+12
| | | | Reviewed-by: Dave Airlie <[email protected]>
* i965/fs: Lower arithmetic instructions with register regions of unsupported ↵Francisco Jerez2015-08-061-0/+62
| | | | | | | | | | | | | | | | | | | | | | width. This extends the SIMD lowering pass to enforce the hardware limitation that no directly-addressed source may read more than 2 physical GRFs. One can easily go over this limit when doing 64-bit arithmetic (e.g. FP64 or extended-precision integer MULs) or SIMD32, so it's nice to be able to just emit an instruction of the intended execution size from the visitor and let the lowering pass deal with this restriction transparently. Some hardware arithmetic instructions are not handled here, including all instructions that use the accumulator implicitly (which the SIMD lowering pass deliberately doesn't handle), instructions with non-per-channel sources (e.g. LINE or PLANE) and SEND-like instructions, which need special handling most likely as virtual opcodes. Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Fix fs_inst::regs_read() for sources in the ATTR file.Francisco Jerez2015-08-061-0/+1
| | | | | | | | | | | Otherwise it would crash on Gen8 with scalar VS. The issue can easily be reproduced with the following patch, but I don't see any reason why it wouldn't be possible to end up with an ATTR argument here even without it. CC: [email protected] Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Implement nir_op_imul/umul_high in terms of MULH.Francisco Jerez2015-08-061-31/+2
| | | | | | And get rid of another no16() call. Reviewed-by: Matt Turner <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 13:46:52 +0000