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* dri/common: clear the loaderPrivate pointer in driDestroyDrawableNicolai Hähnle2017-02-061-0/+12
| | | | | | | | | | | | | | | | | | | | The GLX specification says about glXDestroyPixmap: "The storage for the GLX pixmap will be freed when it is not current to any client." We're not really following this language to the letter: some of the storage is freed immediately (in particular, the dri3_drawable, which contains both GLXDRIdrawable and loader_dri3_drawable). So we NULL out the pointers to that freed storage; the previous patches added the corresponding NULL-pointer checks. This fixes memory corruption in piglit ./bin/glx-visuals-depth/stencil -pixmap -auto Cc: 17.0 <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* intel/isl: Rename supports_lossless_compression to supports_ccs_eJason Ekstrand2017-02-023-6/+3
| | | | | | | | | | | | | The term "lossless compression" could potentially mean multisample color compression, single-sample color compression or HiZ because they are all lossless. The term CCS_E, however, has a very precise meaning; in ISL and is only used to refer to single-sample color compression. It's also much shorter which is nice. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* i965: Prevent coverity warningRobert Foss2017-02-011-0/+1
| | | | | | | | | | | | Add assert checking that num_sources is never larger than 3. This prevents Coverity from concluding that the unhandled cases of num_sources not being 0-3 are relevant. Coverity-Id: 1399480-1399489 Signed-off-by: Robert Foss <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: Fix nir_op_fsign of absolute value.Francisco Jerez2017-01-311-1/+8
| | | | | | | | | | This does point at the front-end emitting silly code that could have been optimized out, but the current fsign implementation would emit bogus IR if abs was set for the argument (because it would apply the abs modifier on an unsigned integer type), and we shouldn't rely on the upper layer's optimization passes for correctness. Reviewed-by: Ian Romanick <[email protected]>
* i965: Support the force_glsl_version driconf option.Kenneth Graunke2017-01-292-0/+4
| | | | | | | | | Gallium drivers have had this for a while. It makes sense to support it consistently across drivers, so expose it in i965 as well. Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix check for negative pitch in can_do_fast_copy_blit().Kenneth Graunke2017-01-291-6/+4
| | | | | | | | | | | | | At this point, the pitch is in bytes. We haven't yet divided the pitch by 4 for tiled surfaces, so abs(pitch) may be larger than 32K. This means the bit 15 trick won't work. The caller now has signed integers anyway, so just pass those through and do the obvious check. Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: add assert to while_jumps_before_offset()Timothy Arceri2017-01-301-0/+1
| | | | | | | jip should always be negative here as its the result of do instruction - while instruction. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: fix up asserts in brw_inst_set_jip()Timothy Arceri2017-01-301-2/+2
| | | | | | | We are casting from a signed 32bit int to an unsigned 16bit int so shift 15 bits rather than 16. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Unbind deleted shaders from brw_context, fixing malloc heisenbug.Kenneth Graunke2017-01-271-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Applications may delete a shader program, create a new one, and bind it before the next draw. With terrible luck, malloc may randomly return a chunk of memory for the new gl_program that happened to be the exact same pointer as our previously bound gl_program. In this case, our logic to detect new programs in brw_upload_pipeline_state() would break: if (brw->vertex_program != ctx->VertexProgram._Current) { brw->vertex_program = ctx->VertexProgram._Current; brw->ctx.NewDriverState |= BRW_NEW_VERTEX_PROGRAM; } Because the pointer is the same, we'd think it was the same program. But it could be wildly different - a different stage altogether, different sets of resources, and so on. This causes utter chaos. As unlikely as this seems, I believe I hit this when running a subset of the CTS in a loop, in a group of tests that churns through simple programs, deleting and rebuilding them. Presumably malloc uses a bucketing cache of sorts, and so freeing up a gl_program and allocating a new one fairly quickly causes it to reuse that memory. The result was that brw->vertex_program->info.num_ssbos claimed the program had SSBOs, while brw->vs.base.prog_data.binding_table claimed that there were none. This was crazy, because the binding table is calculated from info.num_ssbos - the shader info appeared to change between shader compile time and draw time. Careful use of watchpoints revealed that it was being clobbered by rzalloc's memset when building an entirely different program... Fortunately, our 0xd0d0d0d0 canary for unused binding table entries caused us to crash out of bounds when trying to upload SSBOs, or we may have never discovered this heisenbug. Fixes crashes in GL45-CTS.compute_shader.sso-case2 when using a hacked cts-runner that only runs GL45-CTS.compute_shader.s* in EGL config ID 5 at 64x64 in a loop with 100 iterations. Cc: "17.0 13.0 12.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/sync: Implement fences based on Linux sync_fileChad Versace2017-01-271-3/+159
| | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a new type of struct brw_fence, one that is based struct sync_file. This completes support for EGL_ANDROID_native_fence_sync. * Background Linux 4.7 added a new file type, struct sync_file. See commit 460bfc41fd52959311ed0328163f785e023857af Author: Gustavo Padovan <[email protected]> Date: Thu Apr 28 10:46:57 2016 -0300 Subject: dma-buf/sync_file: de-stage sync_file headers A sync file is a cross-driver explicit synchronization primitive. In a sense, sync_file's relation to synchronization is similar to dma_buf's relation to memory: both are primitives that can be imported and exported across drivers (at least in theory). Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/sync: Rename brw_fence_insert()Chad Versace2017-01-271-3/+3
| | | | | | | | | | | | | Rename to brw_fence_insert_locked(). This is correct because the fence's mutex is effectively locked, as all callers are also *creators* of the fence, and have not yet returned the new fence. This reduces noise in the next patch, which defines and uses brw_fence_insert(), an unlocked variant. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/sync: Fail sync creation when batchbuffer flush failsChad Versace2017-01-271-6/+28
| | | | | | | | | | | | | | | | Pre-patch, brw_sync.c ignored the return value of intel_batchbuffer_flush(). When intel_batchbuffer_flush() fails during eglCreateSync (brw_dri_create_fence), we now give up, cleanup, and return NULL. When it fails during glFenceSync, however, we blindly continue and hope for the best because there does not exist yet a way to tell core GL that sync creation failed. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/sync: Add brw_fence::typeChad Versace2017-01-271-32/+71
| | | | | | | | | | | | This a refactor patch; no expected changed in behavior. Add `enum brw_fence_type` and brw_fence::type. There is only one type currently, BRW_FENCE_TYPE_BO_WAIT. This patch reduces a lot of noise in the next, which adds new type BRW_FENCE_TYPE_SYNC_FD. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Add intel_batchbuffer_flush_fence()Chad Versace2017-01-272-12/+26
| | | | | | | | | A variant of intel_batchbuffer_flush() with parameters for in and out fence fds. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Add intel_screen::has_fence_fdChad Versace2017-01-272-1/+4
| | | | | | | | This bool maps to I915_PARAM_HAS_EXEC_FENCE_FD. Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i915, i965: automake: remove NA include directiveEmil Velikov2017-01-272-2/+0
| | | | | | The path in question (... dri/intel/server) was removed years ago. Signed-off-by: Emil Velikov <[email protected]>
* dri/osmesa: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* dri/swrast: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* radeon, r200: automake: include builddir prior to srcdirEmil Velikov2017-01-272-2/+2
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i915: automake: include builddir prior to srcdirEmil Velikov2017-01-271-1/+1
| | | | | | | Analogous to previous commit. Cc: "12.0 13.0" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965: automake: include builddir prior to srcdirEmil Velikov2017-01-271-3/+3
| | | | | | | | | | The latter can contain stale generated file, which, as-is, we'll end up using. Fixes: bfd17c76c12 "i965: Port INTEL_PRECISE_TRIG=1 to NIR." Cc: "12.0 13.0" <[email protected]> Cc: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* i965: automake: correctly set MKDIR_GENEmil Velikov2017-01-271-0/+1
| | | | | | | | | | | Otherwise we might end up w/o the respective folder (depending on autotools version) and fail at build time. Fixes: bfd17c76c12 "i965: Port INTEL_PRECISE_TRIG=1 to NIR." Cc: "12.0 13.0" <[email protected]> Cc: Kenneth Graunke <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Refactor texture format translationTopi Pohjolainen2017-01-271-6/+3
| | | | | | Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/hiz/gen6: Stop setting false qpitchTopi Pohjolainen2017-01-271-1/+7
| | | | | | | | | | | which is not applicable for "all slices at each lod". Current logic makes one to believe it has some purpose. When miptree layout is calculated brw_miptree_layout_texture_array() sets the qpitch unconditionally but later on ignores it altogether for ALL_SLICES_AT_EACH_LOD. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen6: Remove dead code in hiz setupTopi Pohjolainen2017-01-271-9/+9
| | | | | | | | | Such as comment states for intel_miptree_hiz_buffer::mt, hiz_mt only exists for gen6. In addition, intel_hiz_miptree_buf_create() uses MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD unconditionally. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-273-12/+6
| | | | | | | | | | | | In intel_hiz_miptree_buf_create() intel_miptree_aux_buffer::bo is unconditionally initialised to point to the same buffer object as hiz_mt does. The same goes for intel_miptree_aux_buffer::pitch/qpitch. This will make following patches simpler to read. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/blorp/gen6: Simplify hiz surface setupTopi Pohjolainen2017-01-271-6/+4
| | | | | | | | | | | | In intel_hiz_miptree_buf_create() intel_miptree_aux_buffer::bo is unconditionally initialised to point to the same buffer object as hiz_mt does. Also intel_miptree_aux_buffer::offset is initialised to zero (calloc()). This will make following patches significantly simpler to read. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Remove check for stencil formatTopi Pohjolainen2017-01-271-14/+8
| | | | | | | | There are is no alternative. Reviewed-by: Samuel Iglesias Gons\341lvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Remove check for hiz on earlier gens than SNBTopi Pohjolainen2017-01-272-22/+2
| | | | | | | | | | | | Only caller, brw_workaround_depthstencil_alignment(), returns early for gen6+. While at it, reduce scope for brw_get_depthstencil_tile_masks() as well. Reviewed-by: Samuel Iglesias Gons\341lvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Remove redundant check for null textureTopi Pohjolainen2017-01-271-6/+1
| | | | | | | | | There exact same check earlier in brw_miptree_layout() which intel_miptree_create_layout() in turn calls unconditionally. Reviewed-by: Samuel Iglesias Gons\341lvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Tell when brw_miptree_layout() failsTopi Pohjolainen2017-01-273-7/+10
| | | | | | | | In addition, let intel_miptree_create_layout() release the miptree - it is the allocator. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/meta: Remove unused brw_get_rb_for_slice()Topi Pohjolainen2017-01-272-49/+0
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Samuel Iglesias Gons<C3><A1>lvez <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Make intelEmitCopyBlit not truncate large strides.Kenneth Graunke2017-01-262-11/+7
| | | | | | | | | | | | | | | | | | | When trying to blit larger tiled surfaces, the pitch can be larger than 32768 bytes, which means it won't fit in a GLshort. Passing it in will truncate the stride to 0, which has...surprising results. The pitch can be up to 32,768 DWords, or 128kB. We measure it in bytes, but divide by 4 when programming it. So we need to handle values up to 131,072. Switch from GLshort to int32_t to avoid the truncation. Fixes GL45-CTS.gtf30.GL3Tests.depth_texture.depth_texture_copyteximage at widths greater than 8192. v2: Use int32_t as negative values can be used (Jason). Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Use a UW source type for CS_OPCODE_CS_TERMINATE.Kenneth Graunke2017-01-261-1/+1
| | | | | | | | | | | | SIMD16 compute shaders use a send(16) with mlen 1 for the EOT message, using a source of g127 for the single register. With a UD type, this supposedly could read g128, which doesn't exist, causing the simulator to get cranky. Use a UW type to avoid this. Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Fix fast depth clears for surfaces with a dimension of 16384.Kenneth Graunke2017-01-251-0/+12
| | | | | | | | | | | | | | I hadn't bothered to set this bit because I figured it would just paper over us getting the rectangle wrong. But it turns out that there is a legitimate reason to use it, so let's do so. The alternative would be to chop up 16k clears to multiple 8k clears, which is pointlessly painful. Cc: "17.0" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* i965/blorp: Use the correct ISL format for combined depth/stencilJason Ekstrand2017-01-241-0/+2
| | | | | | | | | | | | | | In brw_blorp_copyteximage, we use the format from the render buffer. This could be a combined depth/stencil format. In this case, we handle stencil properly but we give blorp the wrong ISL format. Specifically, we would give blorp ISL_FORMAT_R32G32B32A32_FLOAT which is the wrong size was causing GPU hangs. Fixes: GL45-CTS.gtf30.GL3Tests.packed_depth_stencil.packed_depth_stencil_copyteximage Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Cc: "13.0 17.0" <[email protected]>
* i965/blorp: Add also depth and stencil buffers to render cacheTopi Pohjolainen2017-01-241-0/+4
| | | | | | | | | | v2 (Jason, Curro): Add stencil also even though it is not enabled yet. Cc: 17.0 <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Use UNUSED to silence unused variable (used in assert).Matt Turner2017-01-231-1/+1
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* dri: allow 16bit R/GR images to be exported via drm buffersRainer Hochecker2017-01-232-0/+10
| | | | | | | This allows eglCreateImageKHR to access P010 surfaces created by vaapi Signed-off-by: Rainer Hochecker <[email protected]> Acked-by: Ben Widawky <[email protected]>
* drirc: remove spurious tabsEric Engestrom2017-01-231-8/+8
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa/glsl/i965: set and get tes layouts directly to and from shader_infoTimothy Arceri2017-01-231-3/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa/glsl: set {clip,cull}_distance_array_size directly in gl_programTimothy Arceri2017-01-231-1/+1
| | | | | | | There are some line wrapping violations here but those lines will get deleted in the following patch. Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: use gl_program for CurrentProgram rather than gl_shader_programTimothy Arceri2017-01-2311-77/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes much more sense and should be more performant in some critical paths such as SSO validation which is called at draw time. Previously the CurrentProgram array could have contained multiple pointers to the same struct which was confusing and we would often need to fish out the information we were really after from the gl_program anyway. Also it was error prone to depend on the _LinkedShader array for programs in current use because a failed linking attempt will lose the infomation about the current program in use which is still valid. V2: fix validate_io() to compare linked_stages rather than the consumer and producer to decide if we are looking at inward facing shader interfaces which don't need validation. Acked-by: Edward O'Callaghan <[email protected]> To avoid build regressions the following 2 patches were squashed in to this commit: mesa/meta: rewrite _mesa_shader_program_use() and _mesa_program_use() These are rewritten to do what the function name suggests, that is _mesa_shader_program_use() sets the use of all stage and _mesa_program_use() sets the use of a single stage. Reviewed-by: Lionel Landwerlin <[email protected]> Acked-by: Edward O'Callaghan <[email protected]> mesa: update active relinked program This likely fixes a subroutine bug were _mesa_shader_program_init_subroutine_defaults() would never have been called for the relinked program as we previously just set _NEW_PROGRAM as dirty and never called the _mesa_use* functions when linking. Acked-by: Edward O'Callaghan <[email protected]>
* Revert "i965: Really don't emit Q or UQ moves on Gen < 8"Matt Turner2017-01-201-8/+0
| | | | | | This reverts commit c95380c4044237d73fb537511667c3c8f658fcee. Acked-by: Kenneth Graunke <[email protected]>
* i965: Select DF type for 64-bit integers on Gen < 8.Matt Turner2017-01-204-10/+12
| | | | | | | | | | | | Gen8 adds Q/UQ types. We attempted to change the types back to DF in the generator (commit c95380c40), but an assertion added in the FP64 series (commit e481dcc3) triggers before that code has a chance to execute. In fact, using Q/UQ in the IR and then changing to DF in the generator would not work in the presence of source modifiers, etc. Fixes: d6fcede6 ("i965: Return Q and UQ types for int64 and uint64") Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Enable ARB_gpu_shader_int64 on Gen8+Ian Romanick2017-01-202-0/+6
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Split SIMD16 CMP of Q and UQ instructionsIan Romanick2017-01-201-14/+29
| | | | | | | This is basically the same as happens for doubles. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Enable 64-bit integer support for almost all unary and binary operationsIan Romanick2017-01-201-10/+0
| | | | | | | | Integer comparison functions (e.g., nir_op_ilt) are handled in the next commit. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Enable uploading 64-bit integer uniformsIan Romanick2017-01-201-1/+3
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add 64-bit integer support for conversions and bitcastsIan Romanick2017-01-202-5/+35
| | | | | | | | | | v2 (idr): Make the "from" type in a cast unsized. This reduces the number of required cast operations at the expensive slightly more complex code. However, this will be a dramatic improvement when other sized integer types are added. Suggested by Connor. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
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