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* i965/fs: Add support for compute-to-mrf in 16-wide mode.Eric Anholt2011-04-261-11/+52
| | | | | | | | | This is more painful than instruction scheduling, as we have to compare two MRF writes to see if they coincide, and have to handle partial GRF writes before that (for example, the result of a math instruction written to color). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Typo fix a comment.Eric Anholt2011-04-261-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Enable constant propagation in 16-wide.Eric Anholt2011-04-261-5/+3
| | | | | | | All that needed fixing was skipping the newly-possible uncompressed/sechalf partial GRF constant writes. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix and enable the instruction scheduler for 16-wide.Eric Anholt2011-04-261-8/+42
| | | | | | | | | | Most of the work of the scheduler is agnostic to wide dispatch. It operates on our virtual GRF file, which means instructions are generally referring to 8 or 16 wide naturally. For the MRF file management we're trying to track the actual hardware MRF file, so we need to watch if an instruction writes multiple MRFs. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for 16-wide dispatch with uniforms in use.Eric Anholt2011-04-262-8/+53
| | | | | | | | | | | | This is glued in in a bit of an ugly way -- we rely on the uniforms having been set up by 8-wide dispatch, and we just reuse them without the ability to add new uniforms for any reason, since the 8-wide compile is already completed. Today, this all works out because our optimization passes are effectively the same for both and even if they weren't, we don't reduce the set of uniforms pushed after optimization. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add a little whitespace between shader dumping debug.Eric Anholt2011-04-261-1/+5
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for compr4 MRF writes.Eric Anholt2011-04-261-14/+18
| | | | | | | These reduce an emitted (not decoded) instruction per shader on g4x/gen5, but may allow for additional register coalescing as well. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for 16-wide dispatch on gen5.Eric Anholt2011-04-263-12/+93
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add initial support for 16-wide dispatch on gen6.Eric Anholt2011-04-266-81/+210
| | | | | | | | | At this point it doesn't do uniforms, which have to be laid out the same between 8 and 16. Other than that, it supports everything but flow control, which was the thing that forced us to choose 8-wide for general GLSL support. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for discard instructions in 16-wide mode.Eric Anholt2011-04-261-0/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for math instructions in 16-wide mode.Eric Anholt2011-04-263-14/+45
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix interference calculation of pixel_[xy] in 16-wide.Eric Anholt2011-04-261-0/+23
| | | | | | Fixes glsl-fs-ceil in that mode, which produced the code in the comment. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Disable some optimization passes under 16-wide for now.Eric Anholt2011-04-262-0/+15
| | | | | | | These are fixable for 16, but that can wait until after it's basically working. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for 16-wide texturing on gen5+.Eric Anholt2011-04-261-21/+29
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for computing pixel_[xy] in 16-wide.Eric Anholt2011-04-262-10/+46
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for 16-wide dispatch to the register allocator.Eric Anholt2011-04-261-19/+37
| | | | | | | | Note that the virtual grfs are in increments of the dispatch_width, not hardware registers -- this makes the 16-wide emit and 8-wide emit mostly the same. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move the destination reg setup for 8/16 wide to the emit code.Eric Anholt2011-04-264-10/+6
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Use tiling for dri2AllocateBuffer implementationKristian Høgsberg2011-04-261-1/+10
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* intel: Set gen in intelInitScreen, just copy value in intelInitContextKristian Høgsberg2011-04-263-5/+14
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* intel: Use X tiling for DRM EGL ImagesKristian Høgsberg2011-04-261-1/+1
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* i965: Don't double-emit fragment.color writes for MRT with ARB_fp.Eric Anholt2011-04-232-35/+19
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* i965: Fill in the remaining fields of gen5+ sampler default color.Eric Anholt2011-04-231-4/+14
| | | | Still doesn't fix texwrap.
* i965: Fix batch decode for the gen5+ sampler default color.Eric Anholt2011-04-231-6/+24
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* intel: Add support for ARB_sampler_objects.Eric Anholt2011-04-239-63/+85
| | | | | | | | | | | | This extension support consists of replacing "gl_texture_obj->Sampler." with "_mesa_get_samplerobj(ctx, unit)->". One instance of referencing the texture's base sampler remains in the initial miptree allocation, where I'm not sure we have a clear association with any texture unit. Tested with piglit ARB_sampler_objects/sampler-objects. Reviewed-by: Brian Paul <[email protected]>
* i965: Add support for NV_conditional_render.Eric Anholt2011-04-235-0/+17
| | | | | | | | Since we lack hardware support for it, this is a simple matter of checking _mesa_check_conditional_render at the entrypoints, and suppressing it for the metaops where it doesn't apply. Reviewed-by: Brian Paul <[email protected]>
* meta: Don't do conditional rendering on GenerateMipmaps and BlitFramebuffer.Eric Anholt2011-04-231-1/+24
| | | | | | | | | The NV_conditional_render spec calls out specific operations that conditional rendering applies to, which doesn't include these. Fixes NV_conditional_render/generatemipmap on swrast. Reviewed-by: Brian Paul <[email protected]>
* i965: Add support for ARB_texture_compression_rgtc.Eric Anholt2011-04-233-0/+11
| | | | | | | | Tested with rgtc-teximage-0[12]. EXT_texture_compression_rgtc/fbo-generatemipmap-formats fails in NPOT just like S3TC does. Reviewed-by: Brian Paul <[email protected]>
* mesa/gdi: Address compiler warnings.José Fonseca2011-04-232-136/+131
| | | | In particular the function prototypes.
* mesa/gdi: Remove InitCritSections.cpp.José Fonseca2011-04-231-33/+0
| | | | | We are now able to declare global critical sections through other mechanisms so this is useless code.
* Drop fx windows driver.José Fonseca2011-04-233-2299/+0
| | | | Irrelevant now that glide driver was removed.
* scons: Build classic mesa gdi driver.José Fonseca2011-04-236-115/+52
| | | | | | Build as scons platform=windows mesagdi
* osmesa: Fix Mingw build.José Fonseca2011-04-231-16/+1
| | | | | | Build as scons platform=windows osmesa
* scons: Build osmesa.José Fonseca2011-04-232-0/+37
| | | | | | Just type scons osmesa
* r300/compiler: fix up error messageMarek Olšák2011-04-221-2/+2
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* i915: Gut all remaining bits of hardware fogIan Romanick2011-04-214-107/+13
| | | | | | | | | | | None of this ever gets used. Fog is always calculated by a fragment program. Even though the fixed-function fog unit is never used, state updates are still sent to the hardware. Removing those spurious state updates can't hurt performance. Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i915: i915_context::vertex_fog is always I915_FOG_NONE, so kill itIan Romanick2011-04-213-8/+1
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i915: There's always a fragment programIan Romanick2011-04-211-26/+5
| | | | | | | | | | Fragment programs are generated by core Mesa for fixed-function. Because of this, there's no reason to handle cases where there is no fragment program for fog. Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i915: Delete disabled try_pixel_fog pathsIan Romanick2011-04-211-55/+0
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* mesa: Kill gl_fragment_program::FogOption with fireIan Romanick2011-04-211-2/+0
| | | | | | | | | | | | All drivers expect this to always be GL_NONE. Don't let there be any opportunity for a bad value to leak out and infect some unsuspecting driver. If any driver for hardware that had fixed-function per-fragment fog (i915 and perhaps some r300-ish) was ever going to add support, it would have done it by now. Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i915: gl_fragment_program::FogOption is always GL_NONE so don't check itIan Romanick2011-04-212-11/+2
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i965: gl_fragment_program::FogOption is always GL_NONE so don't check itIan Romanick2011-04-211-5/+0
| | | | | | Reviewed-by: Eric Anholt <[email protected]> Acked-by: Corbin Simpson <[email protected]> Acked-by: Alex Deucher <[email protected]>
* i965: Remove dead vertex buffer structs.Kenneth Graunke2011-04-201-25/+0
| | | | We do this OUT_BATCH-style in brw_draw_upload.c.
* intel: Add support for ARB_color_buffer_float.Eric Anholt2011-04-209-10/+28
| | | | Reviewed-by: Brian Paul <[email protected]>
* meta: Add support for ARB_color_buffer_float to _mesa_meta_Clear().Eric Anholt2011-04-201-4/+24
| | | | | | Tested with piglit arb_color_buffer_float-clear. Reviewed-by: Brian Paul <[email protected]>
* meta: Add support for ARB_color_buffer_float to _mesa_meta_DrawPixels.Eric Anholt2011-04-201-0/+28
| | | | | | Tested with piglit arb_color_buffer_float-drawpixels. Reviewed-by: Brian Paul <[email protected]>
* intel: Add support for ARB_texture_float.Eric Anholt2011-04-206-2/+62
| | | | | | | | | | | | For 1 and 2-channel formats the hardware only supports rendering to R and RG. To do I and L render targets we just call them R and everything works out. For A, we would need to rewrite the CC to do the alpha channel's blending on color instead, and send the fragment alpha down the red channel. For LA, there doesn't seem to be any hope, because we can't do independent color/alpha blending while treating the LA surface as RG. Reviewed-by: Brian Paul <[email protected]>
* intel: Add support for blit copies of >32bpp formats.Eric Anholt2011-04-201-0/+11
| | | | | | | | | The blitter only does up 32bpp at a time, so we handle it by mangling coordinates and calling the surface 32bpp. Fixes ARB_texture_rg/fbo-generatemipmap-formats-float with ARB_texture_float. Reviewed-by: Brian Paul <[email protected]>
* r600c: add evergreen big endian supportAlex Deucher2011-04-195-9/+286
| | | | | | Based on Cedric's r6xx/r7xx patch. Signed-off-by: Alex Deucher <[email protected]>
* r600c: add big endian support for r6xx/r7xxCédric Cano2011-04-1911-50/+508
| | | | | Signed-off-by: Cedric Cano <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r200: enable some extensionsMarek Olšák2011-04-191-2/+10
| | | | | | | | Such as: - GL_ARB_half_float_pixel - GL_ARB_vertex_array_object - GL_APPLE_vertex_array_object - GL_EXT_gpu_program_parameters