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* mesa: added _mesa_meta_check_generate_mipmap_fallback()Brian Paul2009-10-022-3/+28
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* i915: Add stub ARB_occlusion_query support under a driconf debug option.Eric Anholt2009-10-012-1/+10
| | | | | This is useful for enabling our GLSL testcases using the 2.0 entrypoints even though we don't have full GL 2.0.
* i915: Add optional support for ARB_fragment_shader under a driconf option.Eric Anholt2009-10-014-3/+15
| | | | | | | | | | Other vendors have enabled ARB_fragment_shader as part of OpenGL 2.0 enablement even on hardware like the 915 with no dynamic branching or dFdx/dFdy support. But for now we'll leave it disabled because we don't do any flattening of ifs or loops, which is rather restrictive. This support is not complete, and may be unstable depending on your shaders. It passes 10/15 of the piglit glsl tests, but hangs on glean glsl1.
* i915: Add support or fallbacks for GLSL fragment shader opcodes.Eric Anholt2009-10-011-4/+158
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* i915: Add support for varying inputs.Eric Anholt2009-10-012-2/+23
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* i915: Enable ARB_vertex_shader for both i915 and i830.Eric Anholt2009-10-014-4/+45
| | | | | | Since the TNL is all done in software anyway, it should be the same to the user who's probably using ARB_vertex_program otherwise, but gives them a nicer programming environment.
* i915: Increase maximum program size to the hardware limits.Eric Anholt2009-10-012-7/+16
| | | | | | This fixes potential heap trashing if the program of choice exceeds limits, and fixes the native instructions limit being lower than what can be used by valid programs.
* i915: Update and translate the fragment program along with state updates.Eric Anholt2009-10-014-14/+26
| | | | | | | Previously, we were doing it in the midst of the pipeline run, which gave an opportunity to enable/disable fallbacks, which is certainly the wrong time to be doing so. This manifested itself in a NULL dereference for PutRow after transitioning out of a fallback during a run_pipeline in glean glsl1.
* Revert "i915: don't validate PS program when falling back to software"Eric Anholt2009-10-011-2/+1
| | | | | | | This reverts commit e7044d552c6d16389447880b8744a51de1cf0199. It prevented the driver from ever recovering from a software fallback due to a program error. The original bug it claimed to fix doesn't appear to exist post-revert.
* i915: Bail when the fragment program has too many total instructions.Eric Anholt2009-10-011-0/+10
| | | | Previously, we'd go trashing the heap.
* i915: Let i915_program_error take a format string, and don't use _mesa_problem.Eric Anholt2009-10-013-12/+24
| | | | | | It's misleading to report things like the program having too many native instructions as a Mesa implementation error, when the program may just be too big for the hardware.
* Merge branch 'mesa_7_6_branch'Brian Paul2009-10-014-2/+68
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| * i965: Fix massive memory allocation for streaming texture usage.Eric Anholt2009-09-303-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | Once we've freed a miptree, we won't see any more state cache requests that would hit the things that pointed at it until we've let the miptree get released back into the BO cache to be reused. By leaving those surface state and binding table pointers that pointed at it around, we would end up with up to (500 * texture size) in memory uselessly consumed by the state cache. Bug #20057 Bug #23530
| * mesa/xlib: fix GLX_RENDER_TYPE queryBrian Paul2009-09-291-2/+2
| | | | | | | | Return GLX_RGBA_TYPE or GLX_COLOR_INDEX_TYPE.
* | r600: use CB_TARGET_MASK instead of CB_SHADER_MASK for setting color maskAndre Maasikas2009-09-291-3/+3
| | | | | | | | | | | | makes blend functions work better Signed-off-by: Dave Airlie <[email protected]>
* | r600: user correct alpha blend factorAndre Maasikas2009-09-291-2/+2
| | | | | | | | Signed-off-by: Dave Airlie <[email protected]>
* | r600: clear position enable bit when when wpos is not used by FPAndre Maasikas2009-09-291-0/+5
| | | | | | | | Makes doom3 alot nicer..
* | meta: Fix invalid PBO access from DrawPixels when trying to just alloc.Eric Anholt2009-09-281-6/+15
| | | | | | | | | | | | | | | | | | This whole reuse of buffers (TexSubImage instead of TexImage, SubData instead of Data) is bad for hardware drivers, but it's even worse when we accidentally try to access the 2x2 PBO to fill the new 16x16 texture we're creating, producing GL errors. Fixes piglit pbo-drawpixels. Bug #14163.
* | intel: Drop my generatemipmap code in favor of the new shared code.Eric Anholt2009-09-288-309/+1
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* | intel: Remove some dead metaops code.Eric Anholt2009-09-287-68/+2
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* | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-282-1/+5
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| * Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-281-1/+4
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| | * i915: Fix GetBufferSubData in the case of a system-memory BO.mesa_7_5_2_rc1Eric Anholt2009-09-241-1/+4
| | | | | | | | | | | | Bug #23760 (crashes in wine)
| | * intel: Mark the FBO as incomplete if there's no intel_renderbuffer for it.Eric Anholt2009-09-211-0/+5
| | | | | | | | | | | | | | | | | | | | | This happens to rendering with textures with a border, which had resulted in a segfault on dereferencing the irb. (cherry-picked from commit 8bba183b9eeb162661a287bf2e118c6dd419dd24)
| * | intel: Handle GL_RGB8 for glCopyTex(Sub)Image.Michel Dänzer2009-09-251-0/+1
| | | | | | | | | | | | Avoids an unnecessary fallback.
* | | r600 : Enable draw_prim.Richard Li2009-09-271-2/+0
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* | | Merge branch 'asm-shader-rework-2'Ian Romanick2009-09-251-0/+1
|\ \ \ | | | | | | | | | | | | | | | | Conflicts: src/mesa/shader/program_parse.tab.c
| * \ \ Merge branch 'master' into asm-shader-rework-2Ian Romanick2009-09-1080-1771/+2506
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/shader/lex.yy.c src/mesa/shader/program_parse.tab.c src/mesa/shader/program_parse.tab.h
| * | | | Enable GL_NV_fragment_program_option for software renderingIan Romanick2009-09-031-0/+1
| | | | | | | | | | | | | | | | | | | | At this point the extension is not fully implemented.
* | | | | radeon: Fix newlines.Michal Krol2009-09-251-14/+14
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* | | | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-255-20/+10
|\ \ \ \ \ | | |_|/ / | |/| | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_clear.c
| * | | | intel: Flush the batch when we're about to subdata into a VBO.mesa_7_6_rc1Eric Anholt2009-09-242-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the clears in openarena with the new metaops clear code, and the new piglit vbo-subdata-sync test. Bug #23857.
| * | | | i965: Clean up some mess with the batch cache.Eric Anholt2009-09-243-18/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Its flagging of extra state that's already flagged by the vtbl new_batch when appropriate was confusing my tracking down of the OA clear bug.
* | | | | mesa: _mesa_meta_GenerateMipmap() now workingBrian Paul2009-09-241-33/+172
| | | | | | | | | | | | | | | | | | | | | | | | | Handles GL_TEXTURE_1D, GL_TEXTURE_2D, GL_TEXTURE_CUBE_MAP. But GL_TEXTURE_3D and texture borders not supported yet.
* | | | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-244-2/+25
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/vbo/vbo_exec_array.c
| * | | | i965: Emit zero initialization for NV VP temporaries as required.Eric Anholt2009-09-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is similar to what r300 does inside the driver, but I've added it as a generic option since it seems most hardware will want it. Fixes piglit nv-init-zero-reg.vpfp and nv-init-zero-addr.vpfp.
| * | | | i965: Remove assert about NV_vp now that it somewhat works.Eric Anholt2009-09-241-2/+0
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| * | | | i965: Load NV program matrices when required.Eric Anholt2009-09-241-0/+3
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| * | | | intel: use default array/element buffers in intel_generate_mipmap()Brian Paul2009-09-241-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there happened to be a bound VBO when intel_generate_mipmap() was called we blew up because of a bad vertex array pointer. Fixes regnumonline, bug 23859.
* | | | | Merge branch 'mesa_7_6_branch'Pauli Nieminen2009-09-242-6/+7
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| * | | | radeon: Fix scissors for r600 KMS.Pauli Nieminen2009-09-242-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Radeon generic scissors code had problem that some of code was using exclusive and some inclusive bottom right corner. Only r600 driver is using exclusive coordinate so changed generic code to pass inclusive coordinate and r600 driver changes BR coordinate to be exclusive.
* | | | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-241-2/+16
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/r600/r700_assembler.c src/mesa/drivers/dri/r600/r700_chip.c src/mesa/drivers/dri/r600/r700_render.c src/mesa/drivers/dri/r600/r700_vertprog.c src/mesa/drivers/dri/r600/r700_vertprog.h src/mesa/drivers/dri/radeon/radeon_span.c
| * | | | r600: add support for CUBE textures, also TXPAndre Maasikas2009-09-242-47/+263
| | | | | | | | | | | | | | | | | | | | seems to work here ...
| * | | | r600: fix typo in the last commitAlex Deucher2009-09-241-5/+5
| | | | | | | | | | | | | | | | | | | | 128 gprs, 256 reg-based consts
| * | | | r600: various cleanupsAlex Deucher2009-09-243-45/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - max texture size is 8k, but mesa doesn't support that at the moment. - attempt to set shader limits to what the hw actually supports - clean up some old r300 cruft - no need to explicitly disable irqs. This is fixed in the drm now. Signed-off-by: Alex Deucher <[email protected]>
| * | | | r600: fix some issues with LIT instructionAndre Maasikas2009-09-241-33/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - MUL_LIT is ALU.Trans instruction - some Trans instructions can take 3 arguments - don't clobber dst.x, use dst.z as temp, it'll get written correct value in last insn - respect source swizzles
| * | | | r600: fix point sizesAlex Deucher2009-09-241-4/+4
| | | | | | | | | | | | | | | | | | | | registers takes radius
| * | | | r600: fix polygon offsetAlex Deucher2009-09-241-3/+8
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| * | | | radeon: don't build non-r600 span code on r600Alex Deucher2009-09-241-1/+5
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| * | | | r600: minor span cleanupsAlex Deucher2009-09-241-4/+3
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