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* radeon: Hack up an implementation of MapBufferRangeIan Romanick2011-08-231-0/+33
* mesa: Fix incorrect access parameter passed to MapBufferIan Romanick2011-08-231-3/+1
* mesa: Remove target parameter from dd_function_table::FlushMappedBufferRangeIan Romanick2011-08-231-1/+1
* intel: Correctly check for read-only mappings in intel_bufferobj_map_rangeIan Romanick2011-08-231-1/+3
* mesa: Remove target parameter from dd_function_table::MapBufferRangeIan Romanick2011-08-232-3/+2
* mesa: Remove target parameter from dd_function_table::GetBufferSubDataIan Romanick2011-08-233-3/+1
* mesa: Remove target parameter from dd_function_table::BufferSubDataIan Romanick2011-08-233-3/+1
* mesa: Remove target parameter from dd_function_table::MapBufferIan Romanick2011-08-239-25/+18
* mesa: Remove target parameter from dd_function_table::UnmapBufferIan Romanick2011-08-239-29/+23
* i965: Fix typo in 2b224d66a01f3ce867fb05558b25749705bbfe7aEric Anholt2011-08-231-1/+1
* i965/gen6+: Use non-normalized coordinates for GL_TEXTURE_RECTANGLE.Eric Anholt2011-08-234-2/+19
* i965: Implement textureSize (TXS) on Gen4.Kenneth Graunke2011-08-233-6/+23
* i965/fs: Implement textureSize (TXS) on Gen5+.Kenneth Graunke2011-08-235-8/+30
* i965/fs: Rudimentary support for non-floating point texture results.Kenneth Graunke2011-08-231-1/+1
* glsl: Add a new ir_txs (textureSize) opcode to ir_texture.Kenneth Graunke2011-08-231-1/+5
* intel: Abort when DRI2 separate stencil handshake failsChad Versace2011-08-221-0/+7
* i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.Kenneth Graunke2011-08-201-0/+3
* i965/fs: Don't double-convert integer/boolean uniforms.Kenneth Graunke2011-08-191-16/+20
* i965/fs: Change incorrect use of 'struct fs_reg' to simply 'fs_reg'.Kenneth Graunke2011-08-191-1/+1
* i965/vs: Implement proper register allocation instead of 1:1 mapping.Eric Anholt2011-08-192-1/+155
* i965/vs: Add simple dead code elimination.Eric Anholt2011-08-193-0/+38
* i965/vs: Copy the live intervals calculation over from the FS.Eric Anholt2011-08-194-0/+139
* i965/vs: Remove stale comment about compressed instructions.Eric Anholt2011-08-191-1/+0
* meta: use fallback mipmap generation for 1D/2D texture arraysBrian Paul2011-08-191-2/+5
* mesa: Declare _mesa_meta_begin()/end() as publicChad Versace2011-08-192-142/+147
* i965/fs: Fix 32-bit integer multiplication.Eric Anholt2011-08-172-1/+22
* xmlpool.h: fix a typoLauri Kasanen2011-08-171-1/+1
* xmlconfig: Make the error message more informativeLauri Kasanen2011-08-171-1/+1
* i965/vs: Fix multiplies to actually do 32-bit multiplies.Eric Anholt2011-08-162-1/+22
* i965/vs: Add support for conversion of FIXED_HW_REG src_reg to/from dst_reg.Eric Anholt2011-08-161-0/+2
* i965/vs: Fix memory leak of ralloc context for the visitor.Eric Anholt2011-08-161-0/+1
* i965/vs: Fix condition code for scalar expression all_equals.Eric Anholt2011-08-161-1/+1
* i965/vs: Don't assertion fail on vertex texturing.Eric Anholt2011-08-161-1/+6
* i965/gen6: Force WHILE exec size to 8.Eric Anholt2011-08-161-4/+2
* i965/vs: Remove remaining use of foreach_iter.Eric Anholt2011-08-162-9/+5
* i965/vs: Fix abs/negate handling on attributes.Eric Anholt2011-08-161-2/+9
* i965/vs: Avoid generating a MOV for most ir_assignment handling.Eric Anholt2011-08-162-0/+73
* i965/vs: Run the shader backend at link time and return compile failures.Eric Anholt2011-08-166-20/+54
* i965: Fix assertion failure on a loop consisting of while (true) { break }.Eric Anholt2011-08-161-1/+1
* i965/vs: Fix the trivial register allocator's failure path.Eric Anholt2011-08-162-3/+5
* i965/vs: Add support for if(any(bvec)) on gen6.Eric Anholt2011-08-161-4/+8
* i965/vs: Add support for GL_FIXED attributes.Eric Anholt2011-08-161-0/+12
* i965/vs: Clamp vertex color outputs when required by ARB_color_buffer_float.Eric Anholt2011-08-161-1/+10
* i965/vs: Fix access of attribute arrays.Eric Anholt2011-08-161-1/+2
* i965/vs: Fix builtin uniform setup.Eric Anholt2011-08-161-3/+2
* i965/vs: Add support for loops.Eric Anholt2011-08-161-32/+21
* i965/vs: Add support for ir_binop_pow.Eric Anholt2011-08-163-7/+70
* i965/vs: Respect the gen6 limitation that math opcodes can't be align16.Eric Anholt2011-08-162-2/+33
* i965/vs: Fix implementation of ir_unop_any.Eric Anholt2011-08-161-1/+3
* i965/vs: Slightly improve the trivial reg allocator to skip unused regs.Eric Anholt2011-08-161-2/+24
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