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* i965: Upload state on primitive switch, don't just prepare it.Eric Anholt2008-11-121-0/+1
| | | | | This was a regression in 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 that broke blender, among other apps.
* i965: Fix VB refcount leak on aperture overflow.Eric Anholt2008-11-121-0/+1
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* i965: Fix up VS max_threads for G4X and removing a magic number.Eric Anholt2008-11-121-2/+14
| | | | | | As far as I can read in the docs, VS threads can be 1:1 with the pairs of VUE handles allocated for them. Also, G4X can run twice as many threads as before (though we won't unless the we bump the preferred URB entries for VS).
* i965: Fix up SF max_threads.Eric Anholt2008-11-121-1/+2
| | | | | | We were dividing the number of URB entries by two to get number of threads, which looks suspiciously like a copy'n'paste-o from brw_vs_state.c. Also, the maximum number of threads is 24, not 12.
* i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads.Eric Anholt2008-11-122-2/+16
| | | | | | | | | The clip thread could potentially deadlock when processing tristrips since being moved back to dual-thread mode, as the two threads could each have 4 VUEs referenced and not be able to allocate another one since SF processing wasn't able to continue (needing 5 entries before it freed 2). In constrained URB mode, similar deadlock could even have occurred with polygons (so we cut back max_threads if we can't handle it any primitive type).
* i965: Update WM maximum threads for G4X.Eric Anholt2008-11-121-2/+7
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* i965: Add a big comment explaining my understanding of URB management.Eric Anholt2008-11-121-1/+38
| | | | | It shouldn't offer anything new over what's in the docs (except for G4X notes), but here it's all in one place.
* intel: reset cliprect_mode to IGNORE_CLIPRECTS.Xiang, Haihao2008-11-111-1/+3
| | | | | | This ensures all batchbuffers have a same cliprect mode after calling _intel_batchbuffer_flush even if there aren't invalid commands in the current batch buffer. (fix bug#18362).
* mesa: restore glapi/ prefix on #includeBrian Paul2008-11-101-1/+1
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* GLX: fix out-of-bounds memory issue in indirect glAreTexturesResident()Brian Paul2008-11-101-17/+17
| | | | | | | | | | | | | | | | See bug 18445. When getting array results, __glXReadReply() always reads a multiple of four bytes. This can cause writing to invalid memory when 'n' is not a multiple of four. Special-case the glAreTexturesResident() functions now. To fix the bug, we use a temporary buffer that's a multiple of four bytes in length. NOTE: this commit also reverts part of commit 919ec22ecf72aa163e1b97d8c7381002131ed32c (glx/x11: Added some #ifdef GLX_DIRECT_RENDERING protection) which directly edited the indirect.c file rather than the python generator! I'm not repairing that issue at this time.
* dri: alloc __DRIscreen object with calloc()Brian Paul2008-11-101-1/+1
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* mesa: rename OPCODE_INT -> OPCODE_TRUNCBrian Paul2008-11-061-4/+4
| | | | Trunc is a more accurate description; there's no type conversion involved.
* i965: Always check vertex program.Xiang, Haihao2008-11-061-1/+4
| | | | | | Now i965 also uses the vertex program created by Mesa Core, but this vertex program is not only depend on mesa state _NEW_PROGRAM, so always check the current vertex program is updated or not. This fixes broken demo cubemap.
* i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong2008-11-052-10/+335
| | | | OPCODE_NOISE4 coming later.
* i965: Clean up stale NDC comment.Eric Anholt2008-11-021-2/+1
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* i965: Avoid vs header computation for negative rhw on G4X.Eric Anholt2008-11-021-3/+3
| | | | This cuts one MOV out when setting a zero header.
* i965: Merge GM45 into the G4X chipset define.Eric Anholt2008-11-029-25/+24
| | | | | The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
* i965: Fix copy'n'paste issue that made brw->urb.constrained useless.Eric Anholt2008-11-021-3/+7
| | | | Also, add a comment explaining what brw->urb.constrained tries to do.
* Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1Keith Packard2008-11-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <[email protected]>
* intel: pixelzoom doesn't apply to glBitmap, so disable the fallback.Eric Anholt2008-10-311-5/+1
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* intel: Remove fallback for glDrawPixels(GL_COLOR_INDEX)Eric Anholt2008-10-311-7/+0
| | | | | GL_COLOR_INDEX mode is just like other normal formats (that is, not depth/stencil) and is uploaded fine by TexImage.
* intel: Add more fallback debugging for glDrawPixels.Eric Anholt2008-10-311-8/+33
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* i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions.Gary Wong2008-10-312-3/+405
| | | | (Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.)
* i965: support destination horiz strides in align1 access mode.Gary Wong2008-10-312-3/+3
| | | | This is required for scatter writes in destination regions to work.
* intel: Fix glDrawPixels with 4d RasterPos.Eric Anholt2008-10-281-4/+9
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* i965: Fix check_aperture calls to cover everything needed for the prim at once.Eric Anholt2008-10-289-81/+133
| | | | | | | | Previously, since my check_aperture API change, we would check each piece of state against the batchbuffer individually, but not all the state against the batchbuffer at once. In addition to not being terribly useful in assuring success, it probably also increased CPU load by calling check_aperture many times per primitive.
* mesa: fix stand-alone glslcompiler buildBrian Paul2008-10-281-6/+2
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* intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt2008-10-2817-292/+272
| | | | | | | This avoids issues with dereferencing stale cliprects around intel_draw_buffer time. Additionally, take advantage of cliprects staying constant for FBOs and DRI2, and emit cliprects in the batchbuffer instead of having to flush batch each time they change.
* i965: Allocate temporaries contiguously with other regs in fragment shaders.Gary Wong2008-10-282-3/+7
| | | | | This is required for threads to be spawned with correctly sized GRF register blocks.
* i965: Fix compiler warning from unused var.Eric Anholt2008-10-271-1/+0
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* i965: Remove dead brw->wrap flag.Eric Anholt2008-10-273-6/+0
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* intel: Use dri_bo_get_tiling to get tiling mode of buffers we get from names.Eric Anholt2008-10-271-26/+17
| | | | | | Previously, we were trying to pass a name to the GEM GET_TILING_IOCTL, which needs a handle, and failing. None of our buffers were tiled yet, but they will be at some point with DRI2 and UXA.
* intel: GL_FALSE on a BO if it won't be modified when mapping this BO. ↵Xiang, Haihao2008-10-261-1/+1
| | | | (thanks Eric).
* i965: don't emit state when dri_bufmgr_check_aperture_space fails.Xiang, Haihao2008-10-242-4/+12
| | | | This ensures there is an unfilled batchbuffer used for emitting states again. Partial fix for #17964.
* intel: fallback for intelEmitCopyBlit.Xiang, Haihao2008-10-241-10/+39
| | | | | Use _mesa_copy_rect instead of BLT operation if dri_bufmgr_check_aperture_space still fails after flushing batchbuffer. Partial fix for #17964.
* i915: fix carsh in i830_emit_state. (bug #17766)Xiang, Haihao2008-10-211-1/+2
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* fix span issue with really old ddx and non-tcl r100 chipsRoland Scheidegger2008-10-161-1/+1
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* i915: Texture instructions use r/t/oC/oD register as texture coordinate.Xiang, Haihao2008-10-131-0/+13
| | | | Fix http://bugs.freedesktop.org/show_bug.cgi?id=16287.
* intel: Add acceleration for glDrawPixels(GL_STENCIL_INDEX).Eric Anholt2008-10-111-1/+196
| | | | | | | | | This is nasty because there's no way in GL to output data to the stencil buffer directly, so we have to do a dance to wrap the depth/stencil buffer in an ARGB renderbuffer. Improves performance of several oglconform testcases by better than a factor of 2.
* intel: GLSL 1.20 is broken in Mesa, so disable it in the i965 driverIan Romanick2008-10-101-0/+4
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* i965: Add missing intel_pixel_draw.c symlink to fix build.Eric Anholt2008-10-101-0/+1
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* i965: Accelerate depth textures with border color.Eric Anholt2008-10-092-6/+20
| | | | | The fallback was introduced to fix bug #16697, but made the test it was fixing run excessively long.
* i965: Actually hook up the accelerated DrawPixels support.Eric Anholt2008-10-093-3/+3
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* i915: Accelerate depth textures with border color.Eric Anholt2008-10-082-8/+16
| | | | | The fallback was introduced to fix bug #16697, but made the test it was fixing run excessively long.
* i965: Add ARB_occlusion_query support.Eric Anholt2008-10-079-52/+331
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* intel: Push flushing for cliprects changes down into the cliprects changes.Eric Anholt2008-10-071-6/+22
| | | | | | This lets us short-circuit when we're leaving the same cliprects in place, which becomes quite common with metaops clears, and may be useful for some of our FBO paths.
* i965: Fix a potential assertion failure.Xiang, Haihao2008-10-081-2/+4
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* i915: Refine the texture indirect lookup accounting.Eric Anholt2008-10-042-3/+25
| | | | | | | | | | | | | Without this, we would reject programs which sampled multiple times from registers defined in the same phase (block of instructions with the same texture indirection count), as each sample would count as a new phase beginning. Instead, keep track of which phases registers were written in, and only bump phase when we're reading from one generated in this phase. On the other hand, we failed to count oC or oD texture samples as being new phases. Bug #17865.
* intel: Don't advertise unsupported extensions on pre-965 hardwareIan Romanick2008-10-031-2/+2
| | | | | | | | | Move GL_ARB_texture_non_power_of_two and GL_ATI_separate_stencil from the generic extension list to the 965-specific list. Neither extension is supported on i830-class hardware, and GL_ATI_separate_stencil is not supported on i915-class hardare. GL_ARB_texture_non_power_of_two is supported on i915-class hardare and is already in the i915-specific list.
* Unify ARB_depth_texture and SGIX_depth_textureIan Romanick2008-10-014-6/+1
| | | | | | | The ARB extension is a superset of the older SGIX extension. Any hardware that can support the SGIX version can also support the ARB version. In Mesa, any driver that supports one also supports the other. This unification just simplifies some bits of code.
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