summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers
Commit message (Collapse)AuthorAgeFilesLines
* i965/fs: Drop our dead push constants before overflowing to pull constants.Eric Anholt2013-10-291-2/+1
| | | | | | | | | | | | | | | | The idea of the original order was that you'd dead code eliminate accesses to push constants. But I've never seen a case of that (nor has shader-db), while we frequently see sparse accesses of large constant arrays that would overflow into pull constants. Cuts pull constant use on csgo, serious sam, planeshift, and the cave: total instructions in shared programs: 1695103 -> 1688795 (-0.37%) instructions in affected programs: 92024 -> 85716 (-6.85%) GAINED: 339 LOST: 0 Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Simplify the shader time code by using atomic counter helpers.Francisco Jerez2013-10-294-41/+7
| | | | Reviewed-by: Paul Berry <[email protected]>
* i965: Add brw_reg constructors taking a dynamically determined vector width.Francisco Jerez2013-10-291-0/+24
| | | | | | | | The MRF variant is going to be used extensively by the atomic counter intrinsics to assemble untyped atomic and surface read messages easily. Reviewed-by: Paul Berry <[email protected]>
* i965/gen7: Implement code generation for untyped surface read instructions.Francisco Jerez2013-10-299-0/+112
|
* i965/gen7: Implement code generation for untyped atomic instructions.Francisco Jerez2013-10-299-0/+130
| | | | Reviewed-by: Paul Berry <[email protected]>
* i965: Implement ABO surface state emission.Francisco Jerez2013-10-297-0/+122
| | | | | | | | | | | | The maximum number of atomic buffer objects is somewhat arbitrary, we can change it in the future easily if it turns out it's not enough... v2: Add comments with the relevant mesa dirty bits. Fix usage of BRW_NEW_UNIFORM_BUFFER in the GS ABO state atom. v3: Update binding table layout diagrams. v4: Resolve conflicts with the recent dynamic surface index assignment changes. Reviewed-by: Paul Berry <[email protected]>
* i965: Define vtbl method that initializes an untyped R/W surface.Francisco Jerez2013-10-292-5/+37
| | | | | | | | And add Gen7 implementation. v2: Fix off by one error in buffer size calculation. Reviewed-by: Paul Berry <[email protected]>
* glsl: Add new atomic_uint built-in GLSL type.Francisco Jerez2013-10-294-0/+6
| | | | | | | | | v2: Fix GLSL version in which the type became available. Add contains_atomic() convenience method. Split off atomic counter comparison error checking to a separate patch that will handle all opaque types. Include new ir_variable fields for atomic types. Reviewed-by: Ian Romanick <[email protected]>
* i965: Handle deallocation of some private ralloc contexts explicitly.Francisco Jerez2013-10-294-4/+4
| | | | | | | | | These ralloc contexts belong to a specific object and are being deallocated manually from the class destructor. Now that we've hooked up destructors to ralloc there's no reason for them to be children of any other context, and doing so might to lead to double frees under some circumstances. The class destructor has all the responsibility of freeing class memory resources now.
* i965/vec4: Reduce working set size of live variables computation.Eric Anholt2013-10-292-23/+28
| | | | | | | | | | | | | | | | Orbital Explorer was generating a 4000 instruction geometry shader, which was taking 275 trips through dead code elimination and register coalescing, each of which updated live variables to get its work done, and invalidated those live variables afterwards. By using bitfields instead of bools (reducing the working set size by a factor of 8) in live variables analysis, it drops from 88% of the profile to 57%, and reduces overall runtime from I-got-bored-and-killed-it (Paul says 3+ minutes) to 10.5 seconds. Compare to f179f419d1d0a03fad36c2b0a58e8b853bae6118 on the FS side. Reviewed-by: Paul Berry <[email protected]>
* i965: Also emit HiZ and Stencil packets when disabling depth on Gen6.Kenneth Graunke2013-10-281-0/+12
| | | | | | | | | | | The normal drawing path does this, and it's necessary on Ivybridge, so let's try it on Sandybridge too. It's not explicitly documented as necessary, but might help with hangs. Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Xinkai Chen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "9.2" <[email protected]>
* i965: Also emit HIER_DEPTH and STENCIL packets when disabling depth.Kenneth Graunke2013-10-281-0/+12
| | | | | | | | | | | | | | | | | From the documentation: "[DevIVB] 3DSTATE_DEPTH_BUFFER must always be programmed along with the other Depth/Stencil state commands(i.e. 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)." We normally do this, but BLORP was failing to do so in the case where it disables depth. Not observed to fix anything yet. Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Xinkai Chen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "9.2" <[email protected]>
* i965: Move post-sync non-zero flush for 3DSTATE_MULTISAMPLE.Kenneth Graunke2013-10-281-3/+3
| | | | | | | | | | | For some reason, we put the flush in the caller, rather than just before emitting the packet. This is more than a cosmetic problem: BLORP calls gen6_emit_3dstate_multisample() directly, and so it missed the flush. Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Xinkai Chen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "9.2" <[email protected]>
* i965: Also guard 3DSTATE_DRAWING_RECTANGLE with a flush in blorp.Kenneth Graunke2013-10-281-0/+3
| | | | | | | | | Non-pipelined commands need this flush. Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Xinkai Chen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "9.2" <[email protected]>
* i965: Emit post-sync non-zero flush before 3DSTATE_DRAWING_RECTANGLE.Kenneth Graunke2013-10-281-0/+4
| | | | | | | | | This is another non-pipelined command that needs a flush on Sandybridge. Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Xinkai Chen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "9.2" <[email protected]>
* i965: Emit post-sync non-zero flush before 3DSTATE_GS_SVB_INDEX.Kenneth Graunke2013-10-281-0/+3
| | | | | | | | | | | | | | | From the comments above intel_emit_post_sync_nonzero_flush: "[DevSNB-C+{W/A}] Before any depth stall flush (including those produced by non-pipelined state commands), software needs to first send a PIPE_CONTROL with no bits set except Post-Sync Operation != 0." This suggests that every non-pipelined (0x79xx) command needs a post-sync non-zero flush before it. Signed-off-by: Kenneth Graunke <[email protected]> Tested-by: Xinkai Chen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "9.2" <[email protected]>
* i965: CS writes/reads should use I915_GEM_INSTRUCTIONDaniel Vetter2013-10-281-2/+2
| | | | | | | | | | | | | | | | Otherwise the gen6 w/a in the kernel won't kick in and the write will land nowhere. Inspired by a patch Ken pointed me at which had the same issue (but isn't yet merged and also for a gen7+ feature). An audit of the entire driver didn't reveal any other case than the one in in the write_reg helper used by the gen6 queryobj code. Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Tested-by: Xinkai Chen <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Cc: "9.2" <[email protected]>
* i965: Do not set bilinear_filter flag in case of multisample blitsAnuj Phogat2013-10-281-1/+1
| | | | | | | | | | | | | | | | Setting bilinear_filter flag in case of multisample blits with GL_LINEAR filter causes incorrect behavior in translate_dst_to_src() function. This broke Modern Warfare (1, 2 and 3) on SNB, IVB and HSW. Tested on SNB and IVB, no Piglit regressions. Trace file of the game (taken with apitrace) works fine with this patch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69078 Cc: [email protected] Signed-off-by: Anuj Phogat <[email protected]> Reported-by: Armin K <[email protected]> Tested-by: Armin K <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Make fs gl_PrimitiveID input work even when there's no gs.Paul Berry2013-10-272-5/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a geometry shader is present, the fragment shader gl_PrimitiveID input acts like an ordinary varying, receiving data from the gs gl_PrimitiveID output. When there's no geometry shader, we have to ask the fixed function SF hardware to provide the primitive ID to the fragment shader instead. Previously, the SF setup code would handle this situation by recognizing that the FS gl_PrimitiveID input didn't match to any VS output; since normally an FS input with no corresponding VS output leads to undefined data, the SF setup code used to just arbitrarily assign it to receive data from attribute 0. This patch changes the SF setup code so that instead of arbitrarily using attribute 0, it assigns the unmatched FS input to receive gl_PrimitiveID. In the case where the FS input really is gl_PrimitiveID, this produces the intended result. In all other cases, no harm is done since GL specifies that the behaviour is undefined. Fixes piglit test primitive-id-no-gs. v2: If an attribute is already being overridden with point coordinates, don't try to also override it with gl_PrimitiveID. This is necessary to avoid regressing piglit tests such as shaders/glsl-fs-pointcoord. Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove ir_txf coord+offset special case in visitorsChris Forbes2013-10-262-65/+16
| | | | | | | Just let it be handled by the lowering pass. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Generalize coord+offset lowering pass for ir_txfChris Forbes2013-10-261-3/+26
| | | | | | | | | | ir_txf expects an ivec* coordinate, and may be larger than ivec2; shuffle things around so that this will work. V2: Fix style nits, use ir_builder Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add lowering pass to fold offset into unnormalized coordsChris Forbes2013-10-264-0/+81
| | | | | | | | | | | | | | | It turns out that nonzero offsets with gsampler2DRect don't work -- they just return garbage. Work around this by folding the offset into the coord. Done as an IR pass rather than yet another hack in the visitors because it's clear what's going on this way. Can possibly reuse this to replace the existing txf coord+offset hacks. V2: Use ir_builder Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add lowering pass for splitting textureGatherOffsetsChris Forbes2013-10-264-0/+92
| | | | | | | | | | | | | | | | Rewrites textureGatherOffsets(s, p, offsets) into gvec4( textureGatherOffset(s, p, offsets[0]).w, textureGatherOffset(s, p, offsets[1]).w, textureGatherOffset(s, p, offsets[2]).w, textureGatherOffset(s, p, offsets[3]).w ) V2: Use ir_builder to be slightly clearer. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add asserts to ensure that ir_tg4 offset arrays are loweredChris Forbes2013-10-262-0/+6
| | | | | | | | | We don't have a message that does 4 independent offsets; a lowering pass needs to lower it to 4 normal gather4s before reaching this point. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for shadow comparitors with gather4Chris Forbes2013-10-262-3/+15
| | | | | | | | Note that gather4_po_c's parameters are too long for SIMD16. It might be worth emitting 2xSIMD8 messages in this case at some point. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Add support for shadow comparitors with gather4Chris Forbes2013-10-262-3/+16
| | | | | | | | | | gather4_c's argument layout is straightforward -- refz just goes on the end. gather4_po_c's layout however -- the array index is replaced with refz. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add Gen7 gather4_c and gather4_po_c message typesChris Forbes2013-10-261-0/+2
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: add support for gather4 with nonconstant offsetsChris Forbes2013-10-261-1/+15
| | | | Signed-off-by: Chris Forbes <[email protected]>
* i965/fs: add support for gather4 with nonconstant offsetsChris Forbes2013-10-261-7/+46
| | | | | | | | V3: fixup crazy check for whether we need to emit the coordinate after custom handling. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: relax brw_texture_offset assertChris Forbes2013-10-264-5/+10
| | | | | | | | Some texturing ops are about to have nonconstant offset support; the offset in the header in these cases should be zero. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Add SHADER_OPCODE_TG4_OFFSET for gather with nonconstant offsets.Chris Forbes2013-10-266-3/+20
| | | | | | | | | The generator code ends up clearer this way than if we had to sniff via the message length. Implemented via the gather4_po message in hardware, which is present in Gen7 and later. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: add missing tg4 case in brw_instruction_nameChris Forbes2013-10-261-0/+2
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Weaken the flushing in gen7_end_transform_feedback().Kenneth Graunke2013-10-251-6/+6
| | | | | | | | | | | | Since 062317d6671 (i965: Go back to using the kernel SOL reset feature.) we've been flushing the batch on BeginTransformFeedback(). So it's not necessary to do it on EndTransformFeedback(). A PIPE_CONTROL will work. This makes gen7_end_transform_feedback() exactly the same as the gen6 variant. However, they'll diverge again shortly. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Stop trying to hack around MRF dep chains on gen7+ LIFO scheduling.Eric Anholt2013-10-251-1/+1
| | | | | | | | | | | | | | This was a hack to avoid choosing to schedule all texturing before consumption of any texture results due to the way dependency chains worked out in the presence of MRFs. On gen7, we don't have MRFs, so the problem doesn't apply, and this was just badly constraining our scheduling. total instructions in shared programs: 1615306 -> 1612534 (-0.17%) instructions in affected programs: 9958 -> 7186 (-27.84%) GAINED: 259 LOST: 9 Reviewed-by: Matt Turner <[email protected]>
* i965: Try not to reverse-schedule things when doing LIFO scheduling.Eric Anholt2013-10-251-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LIFO plan was simple: Take the most recently made available instructions, and pick those first. But because of the order we were pushing things onto our list of available-to-schedule instructions, it meant that when a set of instructions was made available at the same time (for example, everything at the start of the program that didn't depend on other instructions) we'd schedule them in reverse order. If you had 10 texture calls in a row in your program, each with independent argument setup, we'd set up the last texture call's args and execute it first, even though we wouldn't be able to consume its results until we'd finished the other 9 texture calls (assuming consumption of texture results happens near each texture call, and combines it with another texture result, which is normal for a convolution shader). To fix this, walk the list for doing LIFO in the order that instructions were originally generated in the program, but choose to push newly-made-available instructions to the other end of the list instead. total instructions in shared programs: 1587242 -> 1586290 (-0.06%) instructions in affected programs: 7801 -> 6849 (-12.20%) GAINED: 76 LOST: 67 Thanks to Chia-I Wu for pointing out the bug in my first version of the patch that made it a huge loss. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Match commutative expressions with reversed arguments.Matt Turner2013-10-251-3/+23
| | | | | | | total instructions in shared programs: 1645011 -> 1644938 (-0.00%) instructions in affected programs: 17543 -> 17470 (-0.42%) Reviewed-by: Eric Anholt <[email protected]>
* i965: s/Muchnik/Muchnick/.Matt Turner2013-10-254-4/+4
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Reduce gl_MaxGeometryInputComponents to 64.Paul Berry2013-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although in principle there is no hardware limitation that prevents gl_MaxGeometryInputComponents from being set to 128 on Gen7, we have the following limitations in the vec4 compiler back end: - Registers assigned to geometry shader inputs can't be spilled or later re-used for any other purpose. - The last 16 registers are set aside for the "MRF hack", meaning they can only be used to send messages, and not for general purpose computation. - Up to 32 registers may be reserved for push constants, even if there is sufficient register pressure to make this impractical. A shader using 128 geometry input components, and having an input type of triangles_adjacency, would use up: - 1 register for r0 (which holds URB handles and various pieces of control information). - 1 register for gl_PrimitiveID. - 102 registers for geometry shader inputs (17 registers per input vertex, assuming DUAL_INSTANCED dispatch mode and allowing for one register of overhead for gl_Position and gl_PointSize, which are present in the URB map even if they are not used). - Up to 32 registers for push constants. - 16 registers for the "MRF hack". That's a total of 152 registers, which is well over the 128 registers the hardware supports. Fortunately, the GLSL 1.50 spec allows us to reduce gl_MaxGeometryInputComponents to 64. Doing that frees up 48 registers, brining the total down to 104 registers, leaving 24 registers available to do computation. Fixes piglit test spec/glsl-1.50/execution/geometry/max-input-components. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/gs: If a DUAL_OBJECT gs would spill, fall back to DUAL_INSTANCED.Paul Berry2013-10-243-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | This is similar to what we do for 16-wide vs 8-wide fragment shaders. First we try compiling the geometry shader in DUAL_OBJECT mode. If we can't do that without spilling, we fall back on DUAL_INSTANCED mode, which should require less spilling (since it uses an interleaved layout of payload registers). In an ideal world we'd fall back to SINGLE mode, which would allow us to interleave general-purpose registers too (resulting in even less likelihood of spilling). But at the moment, the vec4 generator and visitor classes don't have the infrastructure to interleave general purpose registers, so DUAL_INSTANCED is the best we can do. As a side benefit this paves the way for implementing instanced geometry shaders (which are incompatible with DUAL_OBJECT mode). Since most geometry shaders used in piglit testing are small, DUAL_INSTANCED mode won't get exercised very much in a normal piglit run. To force DUAL_INSTANCED mode to be used for all geometry shaders, set INTEL_DEBUG=nodualobj. Reviewed-by: Eric Anholt <[email protected]>
* i965/gs: Fix up gl_PointSize input swizzling for DUAL_INSTANCED gs.Paul Berry2013-10-242-1/+32
| | | | | | | | | | | | | | | | | | | Geometry shaders that run in "DUAL_INSTANCED" mode store their inputs in vec4's. This means that when compiling gl_PointSize input swizzling (a MOV instruction which uses a geometry shader input as both source and destination), we need to do two things: - Set force_writemask_all to ensure that the MOV happens regardless of which channels are enabled. - Set the source register region to <4;4,1> (instead of <0;4,1> to satisfy register region restrictions. v2: move the source register region fixup to the top of vec4_generator::generate_vec4_instruction(), so that it applies to all instructions rather than just MOV. Reviewed-by: Eric Anholt <[email protected]>
* i965/gs: Add the ability to compile a DUAL_INSTANCED geometry shader.Paul Berry2013-10-244-8/+30
| | | | | | Not yet enabled. Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Add the ability to suppress register spilling.Paul Berry2013-10-247-10/+23
| | | | | | | | | In future patches, this will allow us to first try compiling a geometry shader in DUAL_OBJECT mode (which is more efficient but uses more registers) and then if spilling is required, fall back on DUAL_INSTANCED mode. Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: if register allocation fails, don't try to schedule.Paul Berry2013-10-241-1/+1
| | | | | | | | | | | Otherwise the scheduler would be invoked with prog_data->total_grf == 0, causing havoc. In a future patch, this will allow us to try compiling a geometry shader in DUAL_OBJECT mode with spilling disabled, and then fall back to DUAL_INSTANCED mode if that failed. Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Add the ability for attributes to be interleaved.Paul Berry2013-10-243-6/+27
| | | | | | | | | | | | When geometry shaders are operated in "single" or "dual instanced" mode, a single set of geometry shader inputs is interleaved into the thread payload (with each payload register containing a pair of inputs) in order to save register space. This patch modifies vec4_visitor::lower_attributes_to_hw_regs so that it can handle the interleaved format. Reviewed-by: Eric Anholt <[email protected]>
* i965/gs: Set force_writemask_all when setting up g0.Paul Berry2013-10-241-2/+3
| | | | | | | | | | | | | | | | | | All geometry shaders begin this instruction: mov(1) g0.2<1>:ud 0x0:ud { align1 } which sets up GRF0 properly for scratch reads and writes. Since this instruction has a SIMD size of 1, it will only have an effect if the first channel is enabled. In practice, the hardware seems to always dispatch geometry shaders with the first channel enabled, but I can't find anything in the docs to guarantee that. So to be on the safe side, set force_writemask_all on the instruction, which guarantees that it will have the desired effect regardless of which channels are enabled. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gs: Precompile geometry shaders.Paul Berry2013-10-244-0/+48
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Extract function to set up vec4 prog key for precompiling.Paul Berry2013-10-243-14/+27
| | | | | | | | This will allow us to re-use it for precompiling geometry shaders. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Remove uses_clip_distance from program key.Paul Berry2013-10-244-12/+3
| | | | | | | | | | This should never have been in the program key in the first place, since it's determined by the shader source, not by GL state. Change the code to just refer to gl_program::UsesClipDistanceOut directly. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: Move UsesClipDistance from gl_{vertex,geometry}_program into gl_program.Paul Berry2013-10-242-2/+4
| | | | | | | | | | | | This will make it easier for back-ends to share code between geometry shader and vertex shader compilation. Also, it is renamed to "UsesClipDistanceOut" to clarify that (a) in geometry shaders, it refers to the gl_ClipDistance output rather than the gl_ClipDistance input, and (b) it is irrelevant in fragment shaders. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fix gl_MaxCombinedTextureImageUnits.Paul Berry2013-10-241-1/+6
| | | | | | | | | | | | | | | | | | | We've always overriden ctx->Const.{Vertex,Fragment}Program.MaxTextureImageUnits to reflect the number of texture image units supported by the hardware (rather than using the default values assigned by Mesa core) so it seems sensible to do that for GeometryProgram.MaxTextureImageUnits too. We set it to 0 if geometry shaders aren't supported. Once that is done, we can just unconditionally add GeometryProgram.MaxTextureImageUnits to MaxCombinedTextureImageUnits. Fixes piglit test "spec/glsl-1.50/built-in constants/gl_MaxCombinedTextureImageUnits". Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 13:06:27 +0000