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path: root/src/mesa/drivers
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* osmesa: remove unused bpc variableFabio Pedretti2011-12-061-8/+0
* radeon/r200: add RV200 detiling + add an always tiled flagDave Airlie2011-12-063-37/+72
* r200: add Z16 depth detiling.Dave Airlie2011-12-061-0/+105
* r200: handle Z24 depth buffers correctlyDave Airlie2011-12-061-2/+2
* r200: fix cb microtile setupDave Airlie2011-12-061-0/+3
* r200: enable tiling flags on blitter setup.Dave Airlie2011-12-061-0/+10
* i965: Fix incorrect comment about single program flow on Ironlake.Kenneth Graunke2011-12-051-1/+1
* radeon/r200: drop old span depth/stencil code.Dave Airlie2011-12-051-317/+0
* radeon/r200: add draw/stencil buffer detilingDave Airlie2011-12-052-0/+111
* radeon: fix warningsDave Airlie2011-12-051-2/+2
* radeon: use mesa renderbuffer accessors for depth for now.Dave Airlie2011-12-051-4/+5
* radeon: add some tiling support for r100.Dave Airlie2011-12-052-0/+13
* radeon: texture/renderbuffer overhaul.Dave Airlie2011-12-0513-599/+385
* radeon: set texture bits to always emit.Dave Airlie2011-12-051-3/+3
* radeon: update flush according to glXMakeCurrent man pageDave Airlie2011-12-051-2/+15
* radeon: drop border checkDave Airlie2011-12-051-5/+0
* radeon: add a bit more debugging to the blit debug code.Dave Airlie2011-12-051-4/+4
* i965: Fix emit of a MOV with bad destination channel on gen6 math in FPs.Stuart Abercrombie2011-12-021-5/+5
* mesa: rename MESA_FORMAT_RG88_REV to MESA_FORMAT_RG88Brian Paul2011-12-021-1/+1
* mesa: rename MESA_FORMAT_RG88 to MESA_FORMAT_GR88Brian Paul2011-12-023-3/+3
* i965: Make gen6_resolve_implied_move a no-op for MRF sources.Kenneth Graunke2011-12-021-0/+3
* swrast: Fix signed/unsigned problems with negative strides.Mathias Fröhlich2011-12-011-2/+2
* i965/fs: Fix regression in fbo-alphatest-nocolor.Eric Anholt2011-11-301-1/+1
* i965/fs: Make register file enum 0 be the undefined register file.Eric Anholt2011-11-302-8/+25
* i965: Don't perform the precompile on fragment shaders by default.Eric Anholt2011-11-304-2/+10
* i965: Always handle GL_DEPTH_TEXTURE_MODE through the shader.Eric Anholt2011-11-292-32/+30
* i965: Fix EXT_texture_swizzle with a writemask in the FFFS/FP backend.Eric Anholt2011-11-291-6/+16
* i965: Base HW depth format setup based on MESA_FORMAT, not bpp.Eric Anholt2011-11-295-54/+39
* i965: Don't depth test the fake depthbuffer when one isn't present.Eric Anholt2011-11-291-1/+6
* mesa: Make gl_program::InputsRead 64 bits.Mathias Fröhlich2011-11-299-24/+40
* android: pass -std=c99 by defaultChia-I Wu2011-11-262-8/+0
* i965/gen6: Fix GPU hang when using stencil buffer without depthChad Versace2011-11-231-0/+5
* i915: Fix complete texturing regression since 27505a105aEric Anholt2011-11-231-0/+2
* i915: Fix build since hiz merge.Eric Anholt2011-11-236-24/+29
* i915: Move the texture format setup for this driver out of shared code.Eric Anholt2011-11-224-42/+54
* i965: Drop intel_context.c's texture format set up for this driver.Eric Anholt2011-11-221-87/+0
* i965: Add support for ARGB2101010 rendering.Eric Anholt2011-11-221-1/+1
* i965: Add support for RGBA_16 unorm rendering.Eric Anholt2011-11-221-1/+1
* i965: Add support for half-float formats.Eric Anholt2011-11-221-7/+11
* i965: Reorganize MESA_FORMAT -> BRW_SURFACEFORMAT table.Eric Anholt2011-11-221-48/+146
* i965: Mark texture formats as supported using the surface formats table.Eric Anholt2011-11-221-1/+12
* intel: Improve debug output for begin/finish render texture.Eric Anholt2011-11-221-4/+4
* intel: Remove duplicate test for texture attachment completeness.Eric Anholt2011-11-221-8/+0
* i965: Don't require spans (swrast) support to consider a format FBO complete.Eric Anholt2011-11-221-3/+10
* i965: Use the surface format table to determine render target supportedness.Eric Anholt2011-11-224-60/+95
* intel: Add the context to the render_target_supported() vtbl method.Eric Anholt2011-11-227-8/+10
* i965: Add a table of the surface format information from the PRM.Eric Anholt2011-11-221-0/+204
* Merge branch 'hiz' of ssh://people.freedesktop.org/~chadversary/mesaChad Versace2011-11-2242-792/+2130
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| * i965/gen6: Enable HiZ by defaultChad Versace2011-11-221-6/+2
| * intel: Use separate stencil whenever possibleChad Versace2011-11-222-2/+2
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