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* i965/vec4: Call calculate_cfg() in test programs to avoid crashing.Matt Turner2014-09-242-0/+2
| | | | Reported-by: Mark Janes <[email protected]>
* mesa: Drop _mesa_getenv() wrapper.Matt Turner2014-09-242-14/+14
| | | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* mesa: Use realloc() instead of _mesa_realloc() and remove the latter.Matt Turner2014-09-241-2/+1
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Add and use functions to get next/prev blocks.Matt Turner2014-09-246-20/+73
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Call insert and remove functions from exec_node directly.Matt Turner2014-09-243-14/+11
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Make instruction lists local to the bblocks.Matt Turner2014-09-2412-92/+115
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add note about double-loop macros and break behavior.Matt Turner2014-09-241-0/+6
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Replace initialization loops with memset().Matt Turner2014-09-242-15/+5
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Don't iterate between blocks with inst->next/prev.Matt Turner2014-09-241-21/+9
| | | | | | The register coalescing portion of this patch hurts three shaders in Guacamelee by one instruction each, but examining the diff makes me believe that what we were generating was (perhaps harmlessly) incorrect.
* i965/fs: Don't iterate between blocks with inst->next/prev.Matt Turner2014-09-245-47/+34
| | | | | | When instruction lists are per-basic block, this won't work. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add macros to iterate through a block given a starting point.Matt Turner2014-09-241-0/+10
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Make count_to_loop_end() use basic blocks.Matt Turner2014-09-241-15/+16
| | | | | | | When the instructions aren't in a flat list, this wouldn't have worked. Also, this should be faster. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Don't use instruction list after calculating the cfg.Matt Turner2014-09-245-14/+15
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Don't use instruction list after calculating the cfg.Matt Turner2014-09-243-22/+22
| | | | | | | | The only trick is changing a break into a return true in register coalescing, since the macro is actually a double loop, and break will do something different than you expect. (Wish I'd realized that earlier!) Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Remove now unneeded calls to calculate_cfg().Matt Turner2014-09-2412-39/+4
| | | | | | | Now that nothing invalidates the CFG, we can calculate_cfg() immediately after emit_fb_writes()/emit_thread_end() and never again. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Remove cfg-invalidating parameter from invalidate_live_intervals.Matt Turner2014-09-2420-40/+34
| | | | | | Everything has been converted to preserve the CFG. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Preserve the CFG in instruction scheduling.Matt Turner2014-09-241-32/+42
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Preserve CFG in spill_reg().Matt Turner2014-09-244-38/+56
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/vec4: Preserve the CFG in a few more places.Matt Turner2014-09-241-7/+16
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Preserve the CFG in a few more places.Matt Turner2014-09-242-15/+21
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Restructure debug flagsKristian Høgsberg2014-09-242-60/+60
| | | | | | | | | | | This cleans up the debug flags to be consistently indented, use bit shifting instead of hex-values and fixes a bug where the new DEBUG_NO8 flag used the same value as the DEBUG_VUE flag. This was hidden by the numbers not being aligned. Also removes gaps in the range where DEBUG_IOCTL (0x4) and DEBUG_REGION (0x400) used to be. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* mesa: Move register_allocate.c to util.Eric Anholt2014-09-234-4/+4
| | | | | | | | | | | | | The r300 gallium driver is using it outside of the Mesa tree, and I wanted to do so for vc4 as well. Rather than make the multiple-definitions problem even more complicated, just move it to more-shared code. v2: Don't forget to delete the symlink in r300 (review by Matt). Delete more r300-helper references (review by Emil) Don't prefix util/ header inclusion with "util/" (review by Emil) Reviewed-by: Matt Turner <[email protected]> (v1) Reviewed-by: Emil Velikov <[email protected]> (v1)
* meta: Fix error paths in meta_copy_image.cJuha-Pekka Heikkila2014-09-231-0/+9
| | | | | | | | If _mesa_get_tex_image() return NULL there is already error set in context. Other error pats free allocated texture. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* meta: Avoid null access on setup_glsl_msaa_blit_shader()Juha-Pekka Heikkila2014-09-231-11/+13
| | | | | | | On default fallback path there was null access on src_rb Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Add extra null check in intel_bufferobj_alloc()Juha-Pekka Heikkila2014-09-231-0/+3
| | | | | | | Check calloc returned requested memory. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Avoid null access in intelMakeCurrent()Juha-Pekka Heikkila2014-09-231-3/+7
| | | | | | | separate two null checks connected with && to their own if branches. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: in set_read_rb_tex_image() check _mesa_meta_bind_rb_as_tex_image() did ↵Juha-Pekka Heikkila2014-09-232-5/+18
| | | | | | | | | | | succeed Check if _mesa_meta_bind_rb_as_tex_image() did give the texture. If no texture was given there is already either GL_INVALID_VALUE or GL_OUT_OF_MEMORY error set in context. Signed-off-by: Juha-Pekka Heikkila <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i915: Fix black buffers when importing prime fdsAndreas Pokorny2014-09-231-0/+2
| | | | | | | | | Width and Height of the imported image was never initialized from the imported bo. Cc: 10.2 10.3 <[email protected]> Signed-off-by: Andreas Pokorny <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* i965/fs: Remove direct fs_visitor brw_wm_prog_key dependenceJordan Justen2014-09-225-9/+36
| | | | | | | | Instead we store a void pointer to the key, and cast it to brw_wm_prog_key for fragment shader specific code paths. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Use brw_sampler_prog_key_data instead of brw_wm_prog_key::texJordan Justen2014-09-221-12/+29
| | | | | | | | | | This helps: 1. Reduce the need to have fs_visitor::key's type be brw_wm_prog_key* 2. Align the code to allow brw_sampler_prog_key_data to be pulled out of other prog_key types for different stages. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Remove direct fs_visitor brw_wm_prog_data dependenceJordan Justen2014-09-223-21/+56
| | | | | | | | Instead we store a brw_stage_prog_data pointer, and cast it to brw_wm_prog_data for fragment shader specific code paths. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/gen6: Enable GL 3.3 and GLSL 3.30Chris Forbes2014-09-202-9/+2
| | | | | | | | | | | | Tested on my snb-gt2: 4 tests skip->pass in spec/EXT_texture_array 51 tests skip->pass in spec.glsl-3.30 4 tests skip->pass in spec/!OpenGL 3.3 No regressions; no skip->fail changes. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6: enable GLSL 1.50, OpenGL 3.2 and GL_AMD_vertex_shader_layeredSamuel Iglesias Gonsalvez2014-09-192-3/+3
| | | | | | | | | | | | | | | | Geometry shaders was the only thing we needed to enable GLSL 1.50 and OpenGL 3.2 in gen6. v2: Layered clears do not work properly in gen6 with OpenGL 3.2. Kenneth and Jordan realized that for this to work we also need GL_AMD_vertex_shader_layered (which requires OpenGL 3.2, so it could not be enabled before this patch), so we agreed to enable this together with OpenGL 3.2 in this patch. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6/gs: Use a specific implementation of geometry shaders for gen6.Iago Toral Quiroga2014-09-191-20/+33
| | | | | | | | | | | | | In gen6 we will use the geometry shader implementation from gen6_gs_visitor.cpp and keep the implementation in brw_vec4_gs_visitor.cpp for gen7+. Notice that gen6_gs_visitor inherits from brw_vec4_gs_visitor so it is not a completely seprate implementation of geometry shaders. Also, gen6 does not support multiple dispatch modes, its default operation mode is equivalent to gen7's SINGLE mode, so select that in gen6 for consistency. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: upload ubo and pull constants surfaces.Iago Toral Quiroga2014-09-191-0/+2
| | | | | | | | | | | | Uniforms declared as uniform blocks are stored in ubo surfaces and need to be pulled from the geometry shader program so make sure we upload them first and do the same for pull constants. This fixes all piglit tests that use uniform blocks: bin/shader_runner tests/spec/glsl-1.50/uniform_buffer/gs-* Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Enable transform feedback support in geometry shadersSamuel Iglesias Gonsalvez2014-09-192-8/+11
| | | | | | Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Fix binding table clash between TF surfaces and textures.Iago Toral Quiroga2014-09-196-29/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | For gen6 geometry shaders we use the first BRW_MAX_SOL_BINDINGS entries of the binding table for transform feedback surfaces. However, vec4_visitor will setup the binding table so that textures use the same space in the binding table. This is done when calling assign_common_binding_table_offsets(0) as part if its run() method. To fix this clash we add a virtual method to the vec4_visitor hierarchy to assign the binding table offsets, so that we can change this behavior specifically for gen6 geometry shaders by mapping textures right after the first BRW_MAX_SOL_BINDINGS entries. Also, when there is no user-provided geometry shader, we only need to upload the binding table if we have transform feedback, however, in the case of a user-provided geometry shader, we can't only look into transform feedback to make that decision. This fixes multiple piglit tests for textureSize() and texelFetch() when these functions are called from a geometry shader in gen6, like these: bin/textureSize gs sampler2D -fbo -auto bin/texelFetch gs usampler2D -fbo -auto Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Avoid buffering transform feedback varyings twice.Iago Toral Quiroga2014-09-192-106/+83
| | | | | | | | | Currently we buffer transform feedack varyings separately. This patch makes it so that we reuse the values we have already buffered for all the output varyings of the geometry shader instead. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Buffer PSIZ/flags vertex data in gen6_gs_visitorSamuel Iglesias Gonsalvez2014-09-191-38/+41
| | | | | | | | | | | | | | Since geometry shaders can alter the value of varyings packed in the first output VUE slot (PSIZ), we need to buffer it together with all the other vertex data so we can emit the right value for each vertex when we do the URB writes. This fixes the following piglit test in gen6: tests/spec/glsl-1.50/execution/redeclare-pervertex-out-subset-gs.shader_test Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Setup SOL surfaces for user-provided geometry shadersSamuel Iglesias Gonsalvez2014-09-191-38/+81
| | | | | | | | | | Update gen6_gs_binding_table and gen6_sol_surface to use user-provided geometry program information when present. This is necessary to implement transform feedback support. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement transform feedback support in gen6_gs_visitorSamuel Iglesias Gonsalvez2014-09-193-45/+390
| | | | | | | | | | This takes care of generating code required to handle transform feedback. Notice that transform feedback isn't enabled yet, since that requires additional setups in other parts of the code that will come in later patches. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Add an additional parameter to the FF_SYNC opcode.Samuel Iglesias Gonsalvez2014-09-194-8/+19
| | | | | | | | | We will use this parameter in later patches to provide information relevant to transform feedback that needs to be set as part of the FF_SYNC message. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement GS_OPCODE_FF_SYNC_SET_PRIMITIVES opcodeSamuel Iglesias Gonsalvez2014-09-194-0/+46
| | | | | | | | | This opcode will be used when filling FF_SYNC header before emitting vertices and their data. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcodeSamuel Iglesias Gonsalvez2014-09-194-0/+33
| | | | | | | | | This opcode generates code to copy the specified destination index into subregister 5 of the MRF message header. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement GS_OPCODE_SVB_WRITE opcodeSamuel Iglesias Gonsalvez2014-09-194-0/+63
| | | | | | | | | This opcode will be used when sending SVB WRITE messages to save transform feedback outputs into Streamed Vertex Buffers. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Enable texture units and upload sampler state.Iago Toral Quiroga2014-09-193-2/+3
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Assign geometry shader VUE map properly.Iago Toral Quiroga2014-09-192-7/+7
| | | | | | | | | | So far in gen6 we only used geometry shaders to implement transform feedback in vertex shaders, so we assumed that the VUE map for the geometry shader stage was always the same as for the vertex shader stage. This is no longer true now that we support user provided geometry shaders in gen6 too. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement support for gl_PrimitiveIdIn.Iago Toral Quiroga2014-09-192-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | For this we will need to move PrimitiveID information, delivered in the thread payload in r0.1, to a separate register (we use GS_OPCODE_SET_PRIMITIVE_ID for this), then map the corresponding varying slot to that register in the setup_payload() method. Notice that we cannot use a virtual register as the destination for the PrimitiveID because we need to map all input attributes to hardware registers in setup_payload(), which happens before virtual registers are mapped to hardware registers. We could work around that issue if we were able to compute the first non-payload register in emit_prolog() and move the PrimitiveID information to that register, but we can't because at that point we still don't know the final number uniforms that will be included in the payload. So, what we do is to place PrimitiveID information in r1, which is always delivered as part of the payload but its only populated with data relevant for transform feedback when we set GEN6_GS_SVBI_PAYLOAD_ENABLE in the 3DSTATE_GS state packet. When we implement transform feedback, we wil make sure to move the value of r1 to another register before we overwrite it with the PrimitiveID. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement GS_OPCODE_SET_PRIMITIVE_ID.Iago Toral Quiroga2014-09-194-0/+27
| | | | | | | | | | In gen6 the geometry shader payload includes the PrimitiveID information in r0.1. When the shader code uses glPimitiveIdIn we will have to move this to a separate hardware register where we can map this attribute. This opcode takes the selected destination register and moves r0.1 there. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Handle the case where a geometry shader emits no output.Iago Toral Quiroga2014-09-192-122/+118
| | | | | | | | | | | | | | | | | | In gen6 we need to end the thread differently depending on whether we have emitted at least one vertex or not. In case we did, the EOT message must always include the COMPLETE flag or else the GPU hangs. If we have not produced any output, however, we can't use the COMPLETE flag. This would lead us to end the program with an ENDIF opcode, which we want to avoid (and actually is not permitted since it hits an assertion), so instead what we do is that we always request a new VUE handle every time we do an URB WRITE, even for the last vertex we emit. With this we make sure that whether we have emitted at least one vertex or none at all we have to finish the thread without writing to the URB, which works for both cases by setting the COMPLETE and UNUSED flags in the EOT message. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
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