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* dri/radeon: nuke the remaining references to sareaEmil Velikov2014-08-213-11/+0
| | | | | | | | | Remainder of the dri1 times. Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* dri/radeon: cleanup the radeon_context vtblEmil Velikov2014-08-218-163/+0
| | | | | | | | | | Remove the set-but-unused, and set-but-empty vtable entries. Most likely a leftover from the dri1 days. Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* dri/radeon: drop obsolete radeon_{dri,macros}.h headersEmil Velikov2014-08-217-248/+2
| | | | | | | | | | | | | | | | Both have been unused for at least a couple of years. For example the last user of radeon_macros.h was removed with commit 8c11f0a88300f7bc3f05a12789c781ba0f4b3cc6 Author: Eric Anholt <[email protected]> Date: Fri Oct 14 13:27:02 2011 -0700 radeon: Drop the legacy BO manager code. Cc: Marek Olšák <[email protected]> Cc: Michel Dänzer <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* i965,meta: Stop unlocking the texture to try and prevent deadlocks.Kenneth Graunke2014-08-201-4/+0
| | | | | | | | | | Unlocking the texture is not safe: another thread could come in and grab it. Now that we use a recursive mutex, this should work. This also fixes texture lock deadlocks in the new meta fast clear path. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Tested-by: Chris Forbes <[email protected]>
* i965/vec4: Allow reswizzling writemasks when swizzle is single-valued.Matt Turner2014-08-201-27/+33
| | | | | total instructions in shared programs: 4288033 -> 4266151 (-0.51%) instructions in affected programs: 930915 -> 909033 (-2.35%)
* i965: Flush the RC and TC before doing a fast clear resolveKristian Høgsberg2014-08-191-2/+2
| | | | | | | | | | | | | | | | | | | | The docs say "When performing a render target resolve, PIPE_CONTROL with end of pipe sync must be delivered.", which doesn't actually tell us whether we need to do it before or after. Blorp did it before and after, and doing it before certainly makes sense. The resolve operation needs to read from the MCS and if we don't flush the render cache it won't get up-to-date data. On the other hand, doing it after should not be necessary, since we call brw_render_cache_set_check_flush() after the resolve. Fixes rendering corruption in kwin's cover switch effect and various steam games. Missing flush spotted by Ken. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Signed-off-by: Kristian Høgsberg <[email protected]>
* i965: Enable ARB_conditional_render_inverted on Gen6+.Chris Forbes2014-08-201-0/+1
| | | | | | | | The extension requires GL 3.0, so enable on just the generations exposing that. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* i965/vec4: Add a pass to reduce swizzles.Matt Turner2014-08-192-0/+99
| | | | | | | total instructions in shared programs: 4344280 -> 4288033 (-1.29%) instructions in affected programs: 397468 -> 341221 (-14.15%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cfg: Add a foreach_block_and_inst_safe macro.Matt Turner2014-08-181-0/+4
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add a foreach_inst_in_block_safe macro.Matt Turner2014-08-181-0/+8
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/cfg: Add a foreach_block_safe macro.Matt Turner2014-08-181-0/+3
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Pass a cfg pointer to generate_{code,assembly}.Matt Turner2014-08-1810-41/+39
| | | | | | | The loop over all instructions is now two-fold, over all of the blocks and all of the instructions in each block. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add and use foreach_block macro.Matt Turner2014-08-1814-143/+119
| | | | | Use this as an opportunity to rename 'block_num' to 'num'. block->num is clear, and block->block_num has always been redundant.
* i965/cfg: Embed link in bblock_t for main block list.Matt Turner2014-08-182-5/+7
| | | | | | | | The next patch adds a foreach_block (block, cfg) macro, which works better if it provides a direct bblock_t pointer, rather than a bblock_link pointer that you have to use to find the actual block. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/fs: Optimize gl_FrontFacing calculation on Gen4/5.Matt Turner2014-08-181-5/+16
| | | | | | Doesn't use fewer instructions, but it does avoid writing the flag register and if we want to switch the representation of true for Gen4/5 in the future, we can just delete the AND instruction.
* i965/fs: Optimize gl_FrontFacing calculation on Gen6+.Matt Turner2014-08-181-6/+15
| | | | | | | total instructions in shared programs: 4288650 -> 4282838 (-0.14%) instructions in affected programs: 595018 -> 589206 (-0.98%) Reviewed-by: Anuj Phogat <[email protected]>
* i965: Use ~0 to represent true on Gen >= 6.Matt Turner2014-08-184-34/+102
| | | | | | | total instructions in shared programs: 4292303 -> 4288650 (-0.09%) instructions in affected programs: 299670 -> 296017 (-1.22%) Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Optimize emit_bool_to_cond_code for logical exprs.Matt Turner2014-08-181-54/+87
| | | | | | | | | AND, OR, and XOR can generate the conditional code directly. total instructions in shared programs: 4293335 -> 4292303 (-0.02%) instructions in affected programs: 121408 -> 120376 (-0.85%) Reviewed-by: Anuj Phogat <[email protected]>
* i965: Use UniformBooleanTrue value for boolean literal true.Matt Turner2014-08-182-2/+6
| | | | Reviewed-by: Anuj Phogat <[email protected]>
* i965: Remove dead call to _mesa_associate_uniform_storage().Matt Turner2014-08-181-6/+0
| | | | | | | | Dead since the call to _mesa_generate_parameters_list_for_uniforms was removed in commit 12751ef2. So this was why all of that code that was supposed to fix up the value of a uniform bool to wasn't happening. Reviewed-by: Anuj Phogat <[email protected]>
* i965: Enable instruction compaction on Gen8+.Matt Turner2014-08-181-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add support for compacting 3-src instructions on Gen8.Matt Turner2014-08-181-0/+185
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add support for compacting 1- and 2-src instructions on Gen8.Matt Turner2014-08-181-13/+35
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen8: Add 3-src instruction compaction tables.Matt Turner2014-08-181-0/+27
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen8: Add instruction compaction tables.Matt Turner2014-08-181-0/+150
| | | | Acked-by: Kenneth Graunke <[email protected]>
* i965: Update JIP/UIP compaction code to operate on bytes.Matt Turner2014-08-181-4/+8
| | | | | | | JIP/UIP were previously in units of compacted instructions. On Gen8 they're in units of bytes. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reverse condition ordering to let us support other gens.Matt Turner2014-08-181-3/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Add CSEL.Matt Turner2014-08-181-0/+1
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* nouveau: don't keep stale pointer to free'd dataIlia Mirkin2014-08-161-0/+1
| | | | | | | | | If ->sys is non-null, we might decide that it's where the data is stored. Reviewed-by: Francisco Jerez <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* nouveau: make sure to invalidate any vbo state as wellIlia Mirkin2014-08-161-0/+1
| | | | | | Reviewed-by: Francisco Jerez <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* i965/gen6: Force ALL_SLICES_AT_EACH_LOD for separate stencil/hizJordan Justen2014-08-151-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For gen6 we will use the ALL_SLICES_AT_EACH_LOD miptree layout for separate stencil/hiz. This is needed because gen6 hiz and separate stencil only support a single miplevel. When accessing the other LODs, we will program a tile aligned offset for the bo. PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK] to [DevSNB]: "The separate stencil buffer does not support mip mapping, thus the storage for LODs other than LOD 0 is not needed." We still allocate storage for the other stencil mip-levels within a single texture, but each mip-level will use non-mip-array spacing. PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer "[DevSNB]: The hierarchical depth buffer does not support the LOD field, it is assumed by hardware to be zero. A separate hierarachical depth buffer is required for each LOD used, and the corresponding buffer’s state delivered to hardware each time a new depth buffer state with modified LOD is delivered." We allocate storage for the other hiz mip-levels within a single texture, but each mip-level will use non-mip-array spacing. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6: Stencil/hiz needs an offset for LOD > 0Jordan Justen2014-08-152-3/+41
| | | | | | | | | | | | Since gen6 separate stencil & hiz only supports LOD0, we need to program an offset to the LOD when emitting the separate stencil/hiz. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6: Force tile alignment for each stencil/hiz LODJordan Justen2014-08-151-3/+36
| | | | | | | | | | | | | | | | Gen6 doesn't support multiple miplevels for hiz and stencil. Therefore, we must point to the LOD directly during rendering. But, we also have removed the tile offsets from normal depth surfaces, so we need to align each LOD to a tile boundary for hiz and stencil. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Support array_layout == ALL_SLICES_AT_EACH_LOD for multiple LODsJordan Justen2014-08-151-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously array_layout ALL_SLICES_AT_EACH_LOD was only used for array spacing lod0 on gen7+ and therefore was only used with a single mip level. gen6 separate stencil & hiz only support LOD0, so we need to allocate the miptree similar to gen7+ array spacing lod0, except we also need space for multiple mip levels. (Since OpenGL stencil and depth support multiple LODs.) The miptree is allocated with tightly packed array slice spacing, but we still also pack the miplevels into the region similar to a normal multi mip level packing. A 2D Array texture with 2 slices and multiple LODs would look somewhat like this: +----------+ | | | | +----------+ | | | | +----------+ +---+ +-+ | | +-+ +---+ +-+ | | : +---+ v3: * Use new array_layout enum * ASCII art! Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LODJordan Justen2014-08-157-17/+35
| | | | | | | | | | | | | gen6 does not support multiple miplevels with separate stencil/hiz. Therefore we need to layout its miptree with no mipmap spacing between the slices of each miplevel. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Change mipmap array_spacing_lod0 to array_layout (enum)Jordan Justen2014-08-157-19/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will want to setup gen6 separate stencil and hiz miptrees in a layout that is similar to array_spacing_lod0. This is needed because gen6 hiz and stencil only support a single mip-level. In both use cases (gen7+ LOD0 spacing & gen6 separate stencil/hiz), the array slices will be packed at each LOD without reserving extra space for LODs within each array slice. So, we generalize the name of this field and add comments to indicate the old and new uses. Motivation for the gen6 change comes from the PRM: PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK] to [DevSNB]: "The separate stencil buffer does not support mip mapping, thus the storage for LODs other than LOD 0 is not needed." PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer "[DevSNB]: The hierarchical depth buffer does not support the LOD field, it is assumed by hardware to be zero. A separate hierarachical depth buffer is required for each LOD used, and the corresponding buffer’s state delivered to hardware each time a new depth buffer state with modified LOD is delivered." v2: * Rename array_spacing_lod0 to non_mip_arrays v3: * Instead, replace array_spacing_lod0 with array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2014-08-153-59/+51
| | | | | | | | | | | | | | | | | | | | | | (bf25ee2 for gen6) Previously we would always find the 2D sub-surface of interest, and then program the surface to this location. Now we always program the 3DSTATE_DEPTH_BUFFER at the start of the surface. To select the lod/slice, we utilize the lod & minimum array element fields. We also must disable brw_workaround_depthstencil_alignment for gen >= 6. Now the hardware will handle alignment when rendering to additional slices/LODs. v3: * Set depth_mt bo RELOC offset to 0, as was done in bf25ee2 Signed-off-by: Jordan Justen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56127 Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6 fbo: make unmatched depth/stencil configs return unsupportedJordan Justen2014-08-151-3/+3
| | | | | | | | (f3c886b for gen6) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 blorp depth: calculate base surface width/heightJordan Justen2014-08-151-0/+13
| | | | | | | | | | (e3a49e1 for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate minimum array element being renderedJordan Justen2014-08-152-0/+4
| | | | | | | | | | | (a23cfb8 for gen6) In layered rendering this will be 0. Otherwise it will be the selected slice. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate LOD being rendered toJordan Justen2014-08-152-0/+6
| | | | | | | | | | (08ef1dd for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate depth (array size) for depth surfaceJordan Justen2014-08-152-0/+5
| | | | | | | | | | | | | (bc1acaa for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Note: Cube maps are treated as 2D arrays with 6 times as many array elements as the cube map array would have. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate more specific surface typeJordan Justen2014-08-152-0/+50
| | | | | | | | | | | | | (171e633 for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Note: Cube maps are treated as 2D arrays with 6 times as many array elements as the cube map array would have. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6_depth_state.c: Remove (gen != 6) code pathsJordan Justen2014-08-151-31/+14
| | | | | | | | | Since this code was branched from brw_misc_state.c, it had support for gen != 6. We can now remove this. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Split gen6 depth hiz state out from brwJordan Justen2014-08-154-1/+188
| | | | | | | | | | | | We will program the gen6 hiz depth state differently to enable layered rendering on gen6. v2: * Remove unneeded gen6_emit_depthbuffer as suggested by Topi Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Adjust render height in errata case for MSAAJordan Justen2014-08-151-1/+17
| | | | | | | | | | | | | | | | | | | In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1 (Surface Arrays For all surfaces other than separate stencil buffer): "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value calculated in the equation above , for every other odd Surface Height starting from 1 i.e. 1,5,9,13" Since this Qpitch errata only impacts the sampler, we have to adjust the input for the rendering surface to achieve the same qpitch. For the affected heights, we increment the height by 1 for the rendering surface. Signed-off-by: Jordan Justen <[email protected]> Acked-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Add support for layered renderbuffersJordan Justen2014-08-152-40/+43
| | | | | | | | | | | | | | | | | | | | | | Rather than pointing the surface_state directly at a single sub-image of the texture for rendering, we now point the surface_state at the top level of the texture, and configure the surface_state as needed based on this. v2: * Use SET_FIELD as suggested by Topi * Simplify min_array_element assignment as suggested by Topi v3: * Use irb->layer_count for depth instead of rb->Depth * Make gl_target const * depth - 1, not depth v4: * Merge in dd43900b & b875f39e fixes to prevent 3D texture piglit regressions Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6_surface_state.c: Remove (gen < 6) code pathJordan Justen2014-08-151-22/+0
| | | | | | | | Since this code was branched from brw_wm_surface_state.c, it had support for gen < 6. We can now remove this. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Split gen6 renderbuffer surface state from gen5 and olderJordan Justen2014-08-154-0/+159
| | | | | | | | | We will program the gen6 renderbuffer surface state differently to enable layered rendering on gen6. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Guard access to gl_Layer by extension #ifdefKristian Høgsberg2014-08-151-0/+2
| | | | | | | | | | | Only assign gl_Layer if we have GL_AMD_vertex_shader_layer. Gen6 doesn't (currently) have that extension, but it also doesn't support layered rendering. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Tested-by: Jordan Justen <[email protected]>
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