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* i965: Move dispatch_grf_start_reg and first_curbe_grf into stage_prog_data.Eric Anholt2014-07-0214-35/+36
| | | | | | | I wanted to access this value from stage-generic code, so stop storing it under two different names. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix state flags for gen4/5 CURBE.Eric Anholt2014-07-021-8/+8
| | | | | | | | If we had some NOS affecting VS compilation that resulted in optimization changing the set of constants to be uploaded, we might not have reuploaded the constants. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove a dead define.Eric Anholt2014-07-021-2/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reuse libdrm's header for AUB definitions.Eric Anholt2014-07-024-71/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix stale comments about the state cache.Eric Anholt2014-07-022-2/+9
| | | | | | This changed in the state streaming work years ago. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix stale binding table comment.Eric Anholt2014-07-021-2/+0
| | | | | | | I recently moved the code from the mentioned location right into this file. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Drop the memcmp for finding duplicated CURBE uploads.Eric Anholt2014-07-024-50/+2
| | | | | | | | | | | | | | At this point, the extra copy of the data and memcmp are as expensive as just re-uploading. Note: now that we'll always upload, and brw_constant_buffer watches BRW_NEW_BATCH anyway, we don't need to explicitly unref the old curbe_bo at batch reset time. No significant performance difference on glamor copywinwin10 (n=55), despite that test having a 98% hit rate on the cache. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Reuse intel_upload.c for gen4/5 constant buffers.Eric Anholt2014-07-023-31/+7
| | | | | | No performance difference on glamor with copywinwin10 (n=40) on my gm45. Reviewed-by: Kenneth Graunke <[email protected]>
* xmlconfig/dri: bool -> unsigned charDave Airlie2014-07-023-10/+8
| | | | | | | | | Drop stdbool, due to the X server being a pain and having struct members called bool, although I've sent a patch to fix that we should retain stupidity here. Use unsigned char which is what GLboolean is anyways. Signed-off-by: Dave Airlie <[email protected]>
* i965/fs: Update discard jump to preserve uniform loads via sampler.Cody Northrop2014-07-011-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 17c7ead7 exposed a bug in how uniform loading happens in the presence of discard. It manifested itself in an application as randomly incorrect pixels on the borders of conditional areas. This is due to how discards jump to the end of the shader incorrectly for some channels. The current implementation checks each 2x2 subspan to preserve derivatives. When uniform loading via samplers was turned on, it uses a full execution mask, as stated in lower_uniform_pull_constant_loads(), and only populates four channels of the destination (see generate_uniform_pull_constant_load_gen7()). It happens incorrectly when the first subspan has been jumped over. The series that implemented this optimization was done before the changes to use samplers for uniform loads. Uniform sampler loads use special execution masks and only populate four channels, so we can't jump over those or corruption ensues. This fix only jumps to the end of the shader if all relevant channels are disabled, i.e. all 8 or 16, depending on dispatch. This preserves the original GLbenchmark 2.7 speedup noted in commit beafced2. It changes the shader assembly accordingly: before : (-f0.1.any4h) halt(8) 17 2 null { align1 WE_all 1Q }; after(8) : (-f0.1.any8h) halt(8) 17 2 null { align1 WE_all 1Q }; after(16): (-f0.1.any16h) halt(16) 17 2 null { align1 WE_all 1H }; v2: Cleaned up comments and conditional ordering. v3: Fix typo. Signed-off-by: Cody Northrop <[email protected]> Reviewed-by: Mike Stroyan <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79948
* i965/fs: Mark case unreachable to silence warning.Matt Turner2014-07-011-0/+2
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Use unreachable() instead of unconditional assert().Matt Turner2014-07-0155-324/+182
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa: Make unreachable macro take a string argument.Matt Turner2014-07-014-9/+4
| | | | | | To aid in debugging. Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Remove useless conditionals.Matt Turner2014-07-011-6/+3
| | | | | Setting a couple of bits is the same cost or less as conditionally setting a couple of bits.
* i965/fs: Pass cfg to calculate_live_intervals().Matt Turner2014-07-016-12/+15
| | | | | | | We've often created the CFG immediately before, so use it when available. Reviewed-by: Ian Romanick <[email protected]>
* i965: Mark fields in the live interval classes protected.Matt Turner2014-07-012-16/+19
| | | | | | | | cfg, for instance, is a pointer to a local variable in calculate_live_intervals, certainly not valid after that function has returned. Reviewed-by: Ian Romanick <[email protected]>
* i965: Use typed foreach_in_list_safe instead of foreach_list_safe.Matt Turner2014-07-0111-55/+20
| | | | Acked-by: Ian Romanick <[email protected]>
* i965: Use typed foreach_in_list instead of foreach_list.Matt Turner2014-07-0118-184/+76
| | | | Acked-by: Ian Romanick <[email protected]>
* i965: Add and use foreach_inst_in_block macros.Matt Turner2014-07-017-25/+17
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Use is_head_sentinel() instead of ->prev == NULL.Matt Turner2014-07-011-1/+1
| | | | | | | Makes it more clear what we're doing and requires less knowledge of exec_list. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Add and use foreach_list_typed_safe.Matt Turner2014-07-011-3/+1
| | | | Acked-by: Ian Romanick <[email protected]>
* mesa: Add and use foreach_in_list_use_after.Matt Turner2014-07-011-4/+1
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Mark predicated PLN instructions with dependency hints.Matt Turner2014-06-301-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | To implement the unlit_centroid_workaround, previously we emitted (+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 1Q }; (-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 1Q }; where the flag register contains the channel enable bits from g0. Since the predicates are complementary, the pair of pln instructions write to non-overlapping components of the destination, which is the case that the dependency control hints are designed for. Typically setting dependency control hints on predicated instructions isn't safe (if an instruction doesn't execute due to the predicate, it won't update the scoreboard, leaving it in a bad state) but since we must have at least one channel executing (i.e., +f0 is true for some channel) by virtue of the fact that the thread is running, we can put the +f0 pln instruction last and set the hints: (-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 NoDDClr 1Q }; (+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 NoDDChk 1Q }; Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Predicate PLN instructions used in unlit centroid WA.Matt Turner2014-06-301-6/+14
| | | | | | Maybe lets us skip some PLN instructions if whole subspans are disabled? Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Add no_dd_{clear,check} fields to fs_inst.Matt Turner2014-06-302-6/+10
| | | | | | | And plumb them through. Also make the assert in the generator look like the vec4 one. Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Let sat-prop ignore live ranges if producer already has sat.Matt Turner2014-06-301-4/+7
| | | | | | | | | | | | | | | | | | | This sequence (where both x and w are used afterwards) wasn't handled. mul.sat x, y, z ... mov.sat w, x We assumed that if x was used after the mov.sat, that we couldn't propagate the saturate modifier, but in fact x was already saturated. So ignore the live range check if the producing instruction already saturates its result. Cuts one instruction from hundreds of TF2 shaders. total instructions in shared programs: 1995631 -> 1994951 (-0.03%) instructions in affected programs: 155248 -> 154568 (-0.44%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Pass const references to emit functions.Matt Turner2014-06-302-12/+14
| | | | Cuts 10k of .text and saves a bunch of useless struct copies.
* i965/vec4: Pass const references to instruction functions.Matt Turner2014-06-302-41/+67
| | | | | | | | | | text data bss dec hex filename 4231165 123200 39648 4394013 430c1d i965_dri.so 4186277 123200 39648 4349125 425cc5 i965_dri.so Cuts 43k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Pass const references to vec4_instruction().Matt Turner2014-06-302-6/+7
| | | | | | | | | | text data bss dec hex filename 4244821 123200 39648 4407669 434175 i965_dri.so 4231165 123200 39648 4394013 430c1d i965_dri.so Cuts 13k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Pass const references to instruction functions.Matt Turner2014-06-302-34/+41
| | | | | | | | | | text data bss dec hex filename 4270747 123200 39648 4433595 43a6bb i965_dri.so 4244821 123200 39648 4407669 434175 i965_dri.so Cuts 25k of .text and saves a bunch of useless struct copies. Reviewed-by: Kenneth Graunke <[email protected]>
* loader: Use drirc device_id parameter in complement to DRI_PRIMEAxel Davy2014-07-011-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DRI_PRIME is not very handy, because you have to launch the executable with it set, which is not always easy to do. By using drirc, the user specifies the target executable and the device to use. After that the program will be launched everytime on the target device. For example if .drirc contains: <driconf> <device driver="loader"> <application name="Glmark2" executable="glmark2"> <option name="device_id" value="pci-0000_01_00_0" /> </application> </device> </driconf> Then glmark2 will use if possible the render-node of ID_PATH_TAG pci-0000_01_00_0. v2: Fix compilation issue v3: Add "-lm" and rebase. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* drirc: Add string supportAxel Davy2014-07-012-1/+35
| | | | | Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Axel Davy <[email protected]>
* dri: remove GL types from config queriesDave Airlie2014-07-011-3/+3
| | | | | | | | This in theory changes ABI for the boolean->bool I think, but nothing in the tree uses configQueryb AFAICS. Reviewed-by: Axel Davy <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* dri/xmlconfig: remove GL types.Dave Airlie2014-07-012-100/+100
| | | | | | | | | | This just drops all the GL types from the xmlconfig and use std C types from stdint and stdbool. v2: drop further double and header include. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965/disasm: Fix INTEL_DEBUG=fs on Broadwell for ARB_fp applications.Kenneth Graunke2014-06-301-1/+1
| | | | | | | | | | | Apparently INTEL_DEBUG=fs has crashed on Broadwell for anything using ARB_fragment_program since commit 9cee3ff5. We need to NULL-check the right field. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Cc: "10.2" <[email protected]>
* i965/disasm: Delete gen8_disasm.c.Kenneth Graunke2014-06-303-1031/+0
| | | | | | | | The functionality has been merged into brw_disasm.c; use that instead. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Stop using gen8_disassemble in favor of brw_disassemble.Kenneth Graunke2014-06-308-42/+8
| | | | | | | | | At this point, brw_disassemble can do everything gen8_disassemble can do - and, thanks to the new brw_inst API, it supports all generations. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Improve render target write message disassembly.Kenneth Graunke2014-06-301-30/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we decoded render target write messages as: render ( RT write, 0, 16, 12, 0) mlen 8 rlen 0 which made you remember (or look up) what the numbers meant: 1. The binding table index 2. The raw message control, undecoded: - Last Render Target Select - Slot Group Select - Message Type (SIMD8, normal SIMD16, SIMD16 replicate data, ...) 3. The dataport message type, again (already decoded as "RT write") 4. The write commit bit (0 or 1) Needless to say, having to decipher that yourself is annoying. Now, we do: render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 with optional "Hi" and "WriteCommit" for slot group/write commit. Thanks to the new brw_inst API, we can also stop duplicating code on a per-generation basis. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Rename msg_target to SFID.Kenneth Graunke2014-06-301-12/+8
| | | | | | | | | | We haven't used the name "message target" in a while - there are a lot of things called "target", and it gets confusing. SFID ("Shared Function ID") is the term commonly used in the modern documentation. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Fix typo in RT UNORM write message.Kenneth Graunke2014-06-301-1/+1
| | | | | | | | | The name of this message is "Render Target UNORM Write" (Sandybridge PRM, Volume 4 Part 1, Page 210). Drop the bogus 'c'. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Use Gen6+ SFID case labels.Kenneth Graunke2014-06-301-2/+4
| | | | | | | | | | Most developers will recognize the Gen6+ SFID names more quickly than the Gen4-5 ones. Given that they're the same values, just use the new names. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: "Handle" Gen8+ HF/DF immediate cases.Kenneth Graunke2014-06-301-0/+7
| | | | | | | | | | | We should print something properly, but I'm not sure how to properly print an HF, and we don't have any DFs today to test with. This is at least better than the current Gen8 disassembler, which would simply assert fail. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/disasm: Cut piles of duplicate swizzle printing.Kenneth Graunke2014-06-301-89/+26
| | | | | | | | Making a helper function saves us from cut and pasting this four times. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly decode negate source modifiers on Broadwell.Kenneth Graunke2014-06-301-4/+49
| | | | | | | | | This is a port of Abdiel's 6f9f916b9b042a294813ab0542390846a38739da to brw_disasm.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Improve disassembly of atomic messages on Haswell+.Kenneth Graunke2014-06-301-7/+21
| | | | | | | | | | This backports the atomic message disassembly support from gen8_disasm.c, which additionally offers support for decoding atomic surface read/write messages, and showing SIMD modes and other details. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Actually disassemble Gen7+ URB opcodes.Kenneth Graunke2014-06-301-3/+19
| | | | | | | | | | | I never bothered implementing the disassembler for Gen7+ URB opcodes, so we were just disassembling them as Ironlake/Sandybridge ones. This looked pretty bad when running Paul's GS EndPrimitive tests, as the "write OWord" message was decoded at ff_sync, which doesn't exist. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Decode Broadwell's invm/rsqrtm math functions.Kenneth Graunke2014-06-301-0/+2
| | | | | | | | We don't use these yet, but we may as well disassemble them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.Kenneth Graunke2014-06-301-2/+3
| | | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/disasm: Properly disassemble all32h/any32h align1 predicates.Kenneth Graunke2014-06-301-11/+13
| | | | | | | | | While we're adding things, use symbolic constants rather than magic numbers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add #defines for any32h/all32h predication.Kenneth Graunke2014-06-301-0/+2
| | | | | | | | | | These have existed since Ivybridge. We don't use them today, but the Gen8+ disassembler supports them, and I'd like to use symbolic names rather than magic numbers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
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