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* radeon/r200: move state atom to common headerDave Airlie2009-01-149-137/+103
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* radeon/r200: start splitting out commonalities into separate headersDave Airlie2009-01-1321-425/+279
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* radeon: use bo_wait to wait for all buffers to be rendered toDave Airlie2009-01-131-1/+10
| | | | | Not 100% sure this is correct, but its what Intel does and its better than CP_IDLE.
* radeon/r300: add code to setup r300 vs r500 using pci device from kernelDave Airlie2009-01-111-149/+177
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* r300: disable settexoffset extension on r300Dave Airlie2008-12-221-1/+1
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* radeon: fix library name for consistencyDave Airlie2008-12-221-1/+1
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* radeon: remove start/end offset + cleanup some whitespaceDave Airlie2008-12-225-62/+33
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* radeon: fixup r500 FP emission for new CSDave Airlie2008-12-223-42/+95
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* radeno: hopefully make r200/radeon buildDave Airlie2008-12-212-4/+6
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* radeon: make DRI1 one work with new CS mechanismDave Airlie2008-12-0110-110/+187
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* radeon: cs add print cs callbackJerome Glisse2008-11-161-1/+6
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* radeon: fix pointer danglingJerome Glisse2008-11-166-12/+16
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* radeon: update to libdrm-radeon API changesJerome Glisse2008-11-156-21/+23
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* radeon: dri2 don't forget to free bufferJerome Glisse2008-11-143-1/+77
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* r300: release bo from pixmapJerome Glisse2008-11-143-4/+26
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* r300: convert to new relocations format (see libdrm-radeon)Jerome Glisse2008-11-147-49/+105
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* r300: SetTex extension supportJerome Glisse2008-11-149-19/+113
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* r300: cs + DRI2 supportJerome Glisse2008-11-1421-348/+958
| | | | | If DRI2 is enabled then switch cmd assembly to directly build hw packet.
* r300: bo and cs abstraction.Jerome Glisse2008-11-1436-3343/+3360
| | | | | | | | | | This abstract memory management and command stream building so we can use different backend either legacy one which use old pathway or a new one like with a new memory manager. This works was done by : Nicolai Haehnle Dave Airlie Jerome Glisse
* i965: Upload state on primitive switch, don't just prepare it.Eric Anholt2008-11-121-0/+1
| | | | | This was a regression in 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 that broke blender, among other apps.
* i965: Fix VB refcount leak on aperture overflow.Eric Anholt2008-11-121-0/+1
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* i965: Fix up VS max_threads for G4X and removing a magic number.Eric Anholt2008-11-121-2/+14
| | | | | | As far as I can read in the docs, VS threads can be 1:1 with the pairs of VUE handles allocated for them. Also, G4X can run twice as many threads as before (though we won't unless the we bump the preferred URB entries for VS).
* i965: Fix up SF max_threads.Eric Anholt2008-11-121-1/+2
| | | | | | We were dividing the number of URB entries by two to get number of threads, which looks suspiciously like a copy'n'paste-o from brw_vs_state.c. Also, the maximum number of threads is 24, not 12.
* i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads.Eric Anholt2008-11-122-2/+16
| | | | | | | | | The clip thread could potentially deadlock when processing tristrips since being moved back to dual-thread mode, as the two threads could each have 4 VUEs referenced and not be able to allocate another one since SF processing wasn't able to continue (needing 5 entries before it freed 2). In constrained URB mode, similar deadlock could even have occurred with polygons (so we cut back max_threads if we can't handle it any primitive type).
* i965: Update WM maximum threads for G4X.Eric Anholt2008-11-121-2/+7
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* i965: Add a big comment explaining my understanding of URB management.Eric Anholt2008-11-121-1/+38
| | | | | It shouldn't offer anything new over what's in the docs (except for G4X notes), but here it's all in one place.
* intel: reset cliprect_mode to IGNORE_CLIPRECTS.Xiang, Haihao2008-11-111-1/+3
| | | | | | This ensures all batchbuffers have a same cliprect mode after calling _intel_batchbuffer_flush even if there aren't invalid commands in the current batch buffer. (fix bug#18362).
* mesa: restore glapi/ prefix on #includeBrian Paul2008-11-101-1/+1
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* GLX: fix out-of-bounds memory issue in indirect glAreTexturesResident()Brian Paul2008-11-101-17/+17
| | | | | | | | | | | | | | | | See bug 18445. When getting array results, __glXReadReply() always reads a multiple of four bytes. This can cause writing to invalid memory when 'n' is not a multiple of four. Special-case the glAreTexturesResident() functions now. To fix the bug, we use a temporary buffer that's a multiple of four bytes in length. NOTE: this commit also reverts part of commit 919ec22ecf72aa163e1b97d8c7381002131ed32c (glx/x11: Added some #ifdef GLX_DIRECT_RENDERING protection) which directly edited the indirect.c file rather than the python generator! I'm not repairing that issue at this time.
* dri: alloc __DRIscreen object with calloc()Brian Paul2008-11-101-1/+1
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* mesa: rename OPCODE_INT -> OPCODE_TRUNCBrian Paul2008-11-061-4/+4
| | | | Trunc is a more accurate description; there's no type conversion involved.
* i965: Always check vertex program.Xiang, Haihao2008-11-061-1/+4
| | | | | | Now i965 also uses the vertex program created by Mesa Core, but this vertex program is not only depend on mesa state _NEW_PROGRAM, so always check the current vertex program is updated or not. This fixes broken demo cubemap.
* i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong2008-11-052-10/+335
| | | | OPCODE_NOISE4 coming later.
* i965: Clean up stale NDC comment.Eric Anholt2008-11-021-2/+1
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* i965: Avoid vs header computation for negative rhw on G4X.Eric Anholt2008-11-021-3/+3
| | | | This cuts one MOV out when setting a zero header.
* i965: Merge GM45 into the G4X chipset define.Eric Anholt2008-11-029-25/+24
| | | | | The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
* i965: Fix copy'n'paste issue that made brw->urb.constrained useless.Eric Anholt2008-11-021-3/+7
| | | | Also, add a comment explaining what brw->urb.constrained tries to do.
* Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1Keith Packard2008-11-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <[email protected]>
* intel: pixelzoom doesn't apply to glBitmap, so disable the fallback.Eric Anholt2008-10-311-5/+1
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* intel: Remove fallback for glDrawPixels(GL_COLOR_INDEX)Eric Anholt2008-10-311-7/+0
| | | | | GL_COLOR_INDEX mode is just like other normal formats (that is, not depth/stencil) and is uploaded fine by TexImage.
* intel: Add more fallback debugging for glDrawPixels.Eric Anholt2008-10-311-8/+33
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* i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions.Gary Wong2008-10-312-3/+405
| | | | (Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.)
* i965: support destination horiz strides in align1 access mode.Gary Wong2008-10-312-3/+3
| | | | This is required for scatter writes in destination regions to work.
* intel: Fix glDrawPixels with 4d RasterPos.Eric Anholt2008-10-281-4/+9
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* i965: Fix check_aperture calls to cover everything needed for the prim at once.Eric Anholt2008-10-289-81/+133
| | | | | | | | Previously, since my check_aperture API change, we would check each piece of state against the batchbuffer individually, but not all the state against the batchbuffer at once. In addition to not being terribly useful in assuring success, it probably also increased CPU load by calling check_aperture many times per primitive.
* intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt2008-10-2817-292/+272
| | | | | | | This avoids issues with dereferencing stale cliprects around intel_draw_buffer time. Additionally, take advantage of cliprects staying constant for FBOs and DRI2, and emit cliprects in the batchbuffer instead of having to flush batch each time they change.
* i965: Allocate temporaries contiguously with other regs in fragment shaders.Gary Wong2008-10-282-3/+7
| | | | | This is required for threads to be spawned with correctly sized GRF register blocks.
* i965: Fix compiler warning from unused var.Eric Anholt2008-10-271-1/+0
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* i965: Remove dead brw->wrap flag.Eric Anholt2008-10-273-6/+0
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* intel: Use dri_bo_get_tiling to get tiling mode of buffers we get from names.Eric Anholt2008-10-271-26/+17
| | | | | | Previously, we were trying to pass a name to the GEM GET_TILING_IOCTL, which needs a handle, and failing. None of our buffers were tiled yet, but they will be at some point with DRI2 and UXA.
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