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* i965: Perform HiZ flush/stall prior to HiZ resolvesJason Ekstrand2017-06-071-13/+26
| | | | | Cc: "17.1" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move the pre-depth-clear flush/stalls to intel_hiz_execJason Ekstrand2017-06-072-56/+58
| | | | | Cc: "17.1" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Take a layer range in intel_hiz_execJason Ekstrand2017-06-075-18/+16
| | | | | Cc: "17.1" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand2017-06-0712-135/+70
| | | | | | | | | | | | | | | | | | | | | | | | This commit, out of necessity, makes a number of changes at once: 1) Changes intel_mipmap_tree to store the clear color for both color and depth as an isl_color_value. 2) Changes the depth/stencil emit code to do the format conversion of the depth clear value on Haswell and earlier instead of pulling a uint32_t directly from the miptree. 3) Changes ISL's depth/stencil emit code to perform the format conversion of the depth clear value on Haswell and earlier instead of assuming that the depth value in the float is pre-converted. 4) Changes blorp to pass the depth value through as a float. 5) Changes the Vulkan driver to pass the depth value to blorp as a float rather than a uint. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Fix alpha to one with dual color blending.Kenneth Graunke2017-06-071-13/+44
| | | | | | | | | | | | | | | | | | | The BLEND_STATE documentation says that alpha to one must be disabled when dual color blending is enabled. However, it appears that it simply fails to override src1 alpha to one. We can work around this by leaving alpha to one enabled, but overriding SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO. This appears to be what the other driver does, and it looks like it works despite the documentation saying not to do it. Fixes spec/ext_framebuffer_multisample/alpha-to-one-dual-src-blend * Piglit tests. v2: Add UNUSED to shut up warning on generations which don't use this. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* tree-wide: remove trailing backslashEric Engestrom2017-06-071-1/+1
| | | | | | | | | Simple search for a backslash followed by two newlines. If one of the newlines were to be removed, this would cause issues, so let's just remove these trailing backslashes. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Explicitly disallow tiled memcpy path on Gen4 with swizzling.Chris Wilson2017-06-063-0/+33
| | | | | | | | | | | The manual detiling paths are not prepared to handle Gen4-G45 with swizzling enabled, so explicitly disable them. (They're already disabled because these platforms don't have LLC but a future patch could enable this path). Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Remove brw_bo_map_unsynchronized()Matt Turner2017-06-063-23/+2
| | | | | | Call brw_bo_map() directly. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use unsynchronized mappings for BufferSubData on non-LLCMatt Turner2017-06-061-10/+6
| | | | | | | | | | | Now that unsynchronized maps actually work, we can use them, like we do on LLC platforms. On Broxton, the performance of Unigine Valley 1.1-rc1 is improved by 37.6656% +/- 0.401389% (n=20) at 1280x720/QUALITY_LOW, and by 20.862% +/- 2.20901% (n=3) at 1920x1080/QUALITY_LOW. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make unsynchronized maps unsynchronized on non-LLCMatt Turner2017-06-062-22/+3
| | | | | | | | On Broxton, the performance of Unigine Valley 1.0 is improved by 13.3067% +/- 0.144322% (n=40) at 1280x720/QUALITY_LOW, and by 1.68478% +/- 0.484226% (n=3) at 1920x1080/QUALITY_LOW. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Implement brw_bo_map_unsynchronized() with MAP_ASYNCMatt Turner2017-06-061-40/+9
| | | | | | | | | | | | This way we can let brw_bo_map() choose the best mapping type. Part of the patch inlines map_gtt() into brw_bo_map_gtt() (and removes map_gtt()). brw_bo_map_gtt() just wrapped map_gtt() with locking and a call to set_domain(). map_gtt() is called by brw_bo_map_unsynchronized() to avoid the call to set_domain(). With the MAP_ASYNC flag, we now have the same behavior previously provided by brw_bo_map_unsynchronized(). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Elide call to set_domain() if MAP_ASYNCMatt Turner2017-06-061-4/+8
| | | | | | No functional change (no callers currently pass MAP_ASYNC) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add and use brw_bo_map()Matt Turner2017-06-0616-54/+52
| | | | | | | | | | | | We can encapsulate the logic for choosing the mapping type. This will also help when we add WC mappings. A few functional changes are made in this patch. On non-LLC, what were previously WB mappings are now GTT mappings (in the prefilling debug code in brw_performance_query.c; the shader_time code in brw_program.c; and in the case of an RW mapping in intel_buffer_objects.c). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Drop MAP_READ from some write-only mappingsMatt Turner2017-06-064-4/+4
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pass flags to brw_bo_map_*Matt Turner2017-06-0616-33/+49
| | | | | | | | | | | | | brw_bo_map_cpu() took a write_enable arg, but it wasn't always clear whether we were also planning to read from the buffer. I kept everything semantically identical by passing only MAP_READ or MAP_READ | MAP_WRITE depending on the write_enable argument. The other flags are not used yet, but MAP_ASYNC for instance, will be used in a later patch to remove the need for a separate brw_bo_map_unsynchronized() function. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rename brw_bo_map() -> brw_bo_map_cpu()Matt Turner2017-06-0616-29/+30
| | | | | | | | I'm going to make a new function named brw_bo_map() in a later patch that is responsible for choosing the mapping type, so this patch clears the way. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rename *_virtual -> map_*Matt Turner2017-06-062-31/+31
| | | | | | | I think these are better names, and it reduces the delta between upstream and Chris Wilson's brw-batch branch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pass the map-mode along to intel_mipmap_tree_map_raw()Chris Wilson2017-06-061-13/+16
| | | | | | | | Since we can distinguish when mapping between READ and WRITE, we can pass along the map mode to avoid stalls and flushes where possible. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add a cache_coherent field to brw_boMatt Turner2017-06-063-0/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove unused 'use_resource_streamer' fieldMatt Turner2017-06-061-1/+0
| | | | | | Missing in the resource streamer removal of commit 951f56cd43bc. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove brw_bo's virtual memberMatt Turner2017-06-0617-121/+102
| | | | | | Just return the map from brw_map_bo_* Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove unused brw_bo_map__* functionsMatt Turner2017-06-062-109/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Finalize miptrees before prepare_textureJason Ekstrand2017-06-051-0/+4
| | | | | | | | | In order to do resolves for texture views with different formats, we need intel_texture_object::_Format to be valid. Calling intel_finalize_mipmap_tree can safely be done multiple times in a row and should be a fairly cheap operation. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Order write of query availablity with earlier writesChris Wilson2017-06-031-2/+11
| | | | | | | | | | | | Currently we signal the availabilty of the query result using an unordered pipe-control write. As it is unordered, it may be executed before the write of the query result itself - and so an observer may read the query result too early. Fix this by requesting that the write of the availablity flag is ordered after earlier pipe control writes. Testcase: piglit/arb_query_buffer_object-qbo/*async* Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: Replace 0 with ISL_FORMAT_UNSUPPORTED in format table (v2)Chad Versace2017-06-022-92/+6
| | | | | | | | | | | | | | | | | When given an *unsupported* mesa_format, brw_isl_format_for_mesa_format() returned 0, a *valid* isl_format, ISL_FORMAT_R32G32B32A32_FLOAT. The problem is that brw_isl_format_for_mesa_format's inner table used 0 instead of ISL_FORMAT_UNSUPPORTED to indicate unsupported mesa formats. Some callers of brw_isl_format_for_mesa_format() were aware of this weirdness, and worked around it. This patch removes those workarounds. v2: Ensure that all array elements are initialized to ISL_FORMAT_UNSUPPORTED, even when new formats are added to enum mesa_format, by using an designated range initializer. Reviewed-by: Matt Turner <[email protected]>
* intel/blorp: Handle gen6 stencil/HiZ offsets in the back-endJason Ekstrand2017-06-014-72/+11
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Make get_intratile_offset_el take the element size in bitsJason Ekstrand2017-06-011-1/+1
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Remove the device parameter from isl_tiling_get_infoJason Ekstrand2017-06-011-2/+1
| | | | | | | | | We were only using it for validating that we don't use Ys/Yf on gen8 and earlier. Removing it from isl_tiling_get_info lets us remove it from a bunch of other things that had no business needing a hardware generation. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Rework Sandy Bridge HiZ and stencil layoutsJason Ekstrand2017-06-015-29/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sandy Bridge does not technically support mipmapped depth/stencil. In order to work around this, we allocate what are effectively completely separate images for each miplevel, ensure that they are page-aligned, and manually offset to them. Prior to layered rendering, this was a simple matter of setting a large enough halign/valign. With the advent of layered rendering, however, things got more complicated. Now, things weren't as simple as just handing a surface off to the hardware. Any miplevel of a normally mipmapped surface can be considered as just an array surface given the right qpitch. However, the hardware gives us no capability to specify qpitch so this won't work. Instead, the chosen solution was to use a new "all slices at each LOD" layout which laid things out as a mipmap of arrays rather than an array of mipmaps. This way you can easily offset to any of the miplevels and each is a valid array. Unfortunately, the "all slices at each lod" concept missed one fundamental thing about SNB HiZ and stencil hardware: It doesn't just always act as if you're always working with a non-mipmapped surface, it acts as if you're always working on a non-mipmapped surface of the same size as LOD0. In other words, even though it may only write the upper-left corner of each array slice, the qpitch for the array is for a surface the size of LOD0 of the depth surface. This mistake causes us to under-allocate HiZ and stencil in some cases and also to accidentally allow different miplevels to overlap. Sadly, piglit test coverage didn't quite catch this until I started making changes to the resolve code that caused additional HiZ resolves in certain tests. This commit switches Sandy Bridge HiZ and stencil over to a new scheme that lays out the non-zero miplevels horizontally below LOD0. This way they can all have the same qpitch without interfering with each other. Technically, the miplevels still overlap, but things are spaced out enough that each page is only in the "written area" of one LOD. Cc: "17.0 17.1" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/dri: Fix bad GL error in intel_create_winsys_renderbuffer()Chad Versace2017-06-011-5/+1
| | | | | | | | | | | This function never occurs in the callchain of a GL function. It occurs only in the callchain of eglCreate*Surface and the analogous paths for GLX. Therefore, even if a thread does have a bound GL context, emitting a GL error here is wrong. A misplaced GL error, when no GL call is made, can confuse clients. Cc: [email protected] Reviewed-by: Ian Romanick <[email protected]>
* i965: Cleanup in intel_create_winsys_renderbuffer()Chad Versace2017-06-011-5/+2
| | | | | | | Combine variable declarations and assignments. Trivial cleanup. Reviewed-by: Ian Romanick <[email protected]>
* i965: Remove bad assert on isl_formatChad Versace2017-06-011-1/+0
| | | | | | | translate_tex_format() asserted that isl_format != 0. But 0 is a valid format, ISL_FORMAT_R32G32B32A32_FLOAT. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix return type of translate_tex_format()Chad Versace2017-06-013-6/+6
| | | | | | | | | It returns an isl_format, not GLuint BRW_FORMAT. I updated every translate_tex_format() found by git-grep. No change in behavior. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix return type of brw_isl_format_for_mesa_format() [v2]Chad Versace2017-06-013-8/+10
| | | | | | | | | | | It returns an isl_format, not uint32_t BRW_FORMAT. I updated every brw_isl_format_for_mesa_format() found by git-grep. No change in behavior. v2: Rebased atop Anuj's patch, which has some of the same fixes. Reviewed-by: Jason Ekstrand <[email protected]> (v1)
* i965: Remove an extra semicolonAnuj Phogat2017-06-011-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: Rename brw_format variable names to isl_formatAnuj Phogat2017-06-013-7/+9
| | | | | | | | | | This patch makes non functional changes. Renaming is just to make the code more readable. V2: update the types to "enum isl_format" Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Reject unsupported formats in glEGLImageTargetTexture2D()Chad Versace2017-06-011-0/+4
| | | | | | | | | | If the EGLImage's format is not a supported texture format according to brw_surface_formats.c, then refuse to create the miptree. This follows the precedent in glEGLImageRenderbufferStorage (implemented by intel_image_target_renderbuffer_storage), which rejects the EGLImage's format if is not renderable. Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make 3DSTATE_CONSTANT_BODY on Gen7+ use arrays.Kenneth Graunke2017-06-011-6/+4
| | | | | | This will let us initialize the constant buffers with loops. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Simplify SO_DECL handling.Kenneth Graunke2017-06-011-28/+13
| | | | | | | We can initialize structs directly, avoid some temporaries, and cut out about half of the skip component handling. Reviewed-by: Rafael Antognolli <[email protected]>
* i965: Make a local for linked_xfb->Outputs[i], to shorten things.Kenneth Graunke2017-06-011-9/+10
| | | | | | This seems a bit more readable. Reviewed-by: Rafael Antognolli <[email protected]>
* i965: Move SOL PSIZ hacks from draw time to link time.Kenneth Graunke2017-06-012-22/+40
| | | | | | | | | We can just update the gl_transform_feedback_info fields at link time to make the VUE header fields have the right location and component. Then we don't need to handle them specially at draw time, which is expensive. Reviewed-by: Rafael Antognolli <[email protected]>
* r100: Silence numerous unused this or that warningsIan Romanick2017-05-311-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | radeon_fbo.c: In function ‘radeon_map_renderbuffer_s8z24’: radeon_fbo.c:147:50: warning: unused parameter ‘ctx’ [-Wunused-parameter] radeon_map_renderbuffer_s8z24(struct gl_context *ctx, ^~~ radeon_fbo.c: In function ‘radeon_map_renderbuffer_z16’: radeon_fbo.c:186:48: warning: unused parameter ‘ctx’ [-Wunused-parameter] radeon_map_renderbuffer_z16(struct gl_context *ctx, ^~~ radeon_fbo.c: In function ‘radeon_unmap_renderbuffer_s8z24’: radeon_fbo.c:344:52: warning: unused parameter ‘ctx’ [-Wunused-parameter] radeon_unmap_renderbuffer_s8z24(struct gl_context *ctx, ^~~ radeon_fbo.c: In function ‘radeon_unmap_renderbuffer_z16’: radeon_fbo.c:377:50: warning: unused parameter ‘ctx’ [-Wunused-parameter] radeon_unmap_renderbuffer_z16(struct gl_context *ctx, ^~~ radeon_fbo.c: In function ‘radeon_nop_alloc_storage’: radeon_fbo.c:624:75: warning: unused parameter ‘rb’ [-Wunused-parameter] radeon_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb, ^~ radeon_fbo.c:625:12: warning: unused parameter ‘internalFormat’ [-Wunused-parameter] GLenum internalFormat, GLuint width, GLuint height) ^~~~~~~~~~~~~~ radeon_fbo.c:625:35: warning: unused parameter ‘width’ [-Wunused-parameter] GLenum internalFormat, GLuint width, GLuint height) ^~~~~ radeon_fbo.c:625:49: warning: unused parameter ‘height’ [-Wunused-parameter] GLenum internalFormat, GLuint width, GLuint height) ^~~~~~ radeon_fbo.c: In function ‘radeon_bind_framebuffer’: radeon_fbo.c:696:74: warning: unused parameter ‘fbread’ [-Wunused-parameter] struct gl_framebuffer *fb, struct gl_framebuffer *fbread) ^~~~~~ radeon_fbo.c: In function ‘radeon_validate_framebuffer’: radeon_fbo.c:832:19: warning: unused variable ‘radeon’ [-Wunused-variable] radeonContextPtr radeon = RADEON_CONTEXT(ctx); ^~~~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* r100: Use _mesa_get_format_base_format in radeon_update_wrapperIan Romanick2017-05-311-1/+1
| | | | | | | | | | | | | | The wrapper is for a renderbuffer around a texture. Textures can have formats (e.g., 3) that aren't valide for API generated renderbuffers. _mesa_base_fbo_format will return 0, but _mesa_get_format_base_format will return the base format of RGB. Fixes a crashes in piglit tests fbo-alphatest-formats (all subtests pass) and fbo-colormask-formats (some subtests pass, some fail). Signed-off-by: Ian Romanick <[email protected]> Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* r100,r200: Don't assume glVisual is non-NULL during context creationIan Romanick2017-05-313-3/+1
| | | | | | | | | | | Thanks to EGL_MESA_configless_context, the visual pointer can be NULL. Fixes a segfault (or assertion failure) in piglit's egl-configless-context test. Signed-off-by: Ian Romanick <[email protected]> Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* r100: Don't assume that the base mipmap of a texture existsIan Romanick2017-05-311-4/+10
| | | | | | | | Fixes crashes in piglit's gl-1.2-texture-base-level. Signed-off-by: Ian Romanick <[email protected]> Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Delete dead old-school packing structs.Kenneth Graunke2017-05-301-175/+0
| | | | Trivial.
* i965: Set the "Float Blend Optimization Enable" bit on Gen9+.Kenneth Graunke2017-05-302-1/+4
| | | | | | | | | | | | | | | | | This is woefully undocumented. It's some kind of optimization that avoids unnecessary render target reads when blending with a floating point render target, using independent alpha blending modes. The internal documentation indicates that this bit exists on Cherryview as well, but the other driver doesn't appear to set it on that platform. There's also some confusing wording that indicates that it may exist on Broadwell, but the documentation says it's reserved, so who knows. I was not able to find any workload that benefited from setting this bit, but it seems like a good idea to set it nonetheless. Reviewed-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965: Fix type of brw_context::render_target_format[]Chad Versace2017-05-303-5/+5
| | | | | | | | | It's an array of isl_format, not uint32_t. This patch updates every reference to render_target_format[] git-grep. Trivial cleanup. No change in behavior. Reviewed-by: Tapani Pälli <[email protected]>
* i965: Move func to right comment block in brw_context.hChad Versace2017-05-301-1/+1
| | | | | | | brw_init_surface_formats() is defined in brw_surface_formats.c, not brw_wm_surface_state.c. Reviewed-by: Tapani Pälli <[email protected]>
* i965: Document type of GLuint __DRIimage::formatChad Versace2017-05-301-1/+1
| | | | | | It's either a mesa_format or mesa_array_format. Reviewed-by: Tapani Pälli <[email protected]>
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