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* i965: Set Address Modify Enable in VERTEX_BUFFER on Ivybridge.Kenneth Graunke2011-05-172-0/+4
| | | | | | | | Otherwise, Ivybridge seems to ignore the newly supplied data, giving us rubbish for vertices. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Enable channel masks in Ivybridge's URB_WRITE_HWORD header.Kenneth Graunke2011-05-171-0/+8
| | | | | | | | This shouldn't be done using MRFs, but until I have a proper solution for dealing with MRFs, this allows my hack to keep working. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix the URB write message descriptor on Ivybridge.Kenneth Graunke2011-05-172-2/+29
| | | | | | | The message header is still incorrect, but this is a start. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix render target writes on Ivybridge.Kenneth Graunke2011-05-172-1/+29
| | | | | | | Ivybridge shifts the data port messages by one bit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Mad hacks to avoid using MRFs on Ivybridge.Kenneth Graunke2011-05-171-1/+19
| | | | | | | | | | | | | | | | | Ivybridge's SEND instruction uses GRFs instead of MRFs. Unfortunately, a lot of our code explicitly uses MRFs, and rewriting it would take a fair bit of effort. In the meantime, use a hack: - Change brw_set_dest, brw_set_src0, and brw_set_src1 to implicitly convert any MRFs into the top 16 GRFs. - Enable gen6_resolve_implied_move on Ivybridge: Moving g0 to m0 actually moves it to g111 thanks to the previous hack. It remains to officially reserve these registers so the allocator doesn't try to reuse them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Emit 3DPRIMITIVE Ivybridge-style.Kenneth Graunke2011-05-172-1/+62
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Don't use the GS for breaking down quads on Ivybridge.Kenneth Graunke2011-05-172-3/+3
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Emit extra 0's in 3DSTATE_MULTISAMPLE on Ivybridge.Kenneth Graunke2011-05-171-2/+5
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add depth buffer support on Ivybridge.Kenneth Graunke2011-05-176-5/+140
| | | | | | | | This also disables the HiZ and separate stencil buffers. We still need to implement stencil. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Upload sampler state pointers on Ivybridge.Kenneth Graunke2011-05-174-1/+11
| | | | | | | | Since we currently only support sampling in the fragment shader, we only bother to emit the PS variant. In the future we'll need to emit others. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Disable binding table pointers for unused pipeline stages.Kenneth Graunke2011-05-172-0/+17
| | | | | | | This may not be necessary, but it seems like a good idea. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Upload binding table pointers on Ivybridge.Kenneth Graunke2011-05-174-2/+16
| | | | | | | Ivybridge uses per-stage commands to update binding table pointers. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Split BRW_NEW_BINDING_TABLE dirty bit into one per stage.Kenneth Graunke2011-05-175-15/+27
| | | | | | | | | Ivybridge can update each stage's binding table pointer independently, so we want separate dirty bits. Previous generations can simply subscribe to all three dirty bits and emit as usual. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Explicitly disable unused pipeline stages on Ivybridge.Kenneth Graunke2011-05-175-1/+141
| | | | | | | This may not be strictly necessary, but seems wise. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge VS state.Kenneth Graunke2011-05-174-1/+96
| | | | | | | | | Copied from gen6_vs_state.c; reuses create_vs_constant_bo from there. The 3DSTATE_VS command is identical but 3DSTATE_CONSTANT_VS is not. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge Viewport state setup.Kenneth Graunke2011-05-176-4/+137
| | | | | | | | | | | SF and CLIP viewport state has been combined into SF_CLIP_VIEWPORT; SF_CLIP and CC state pointers can now be uploaded independently. Some portions of the hardware documentation refer to separate upload commands for SF and CLIP; these are outdated and incorrect. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge Clip state setup.Kenneth Graunke2011-05-175-1/+125
| | | | | | | | | | | Copied from gen6_clip_state.c. This enables early culling and sets the necessary fields. Otherwise, it is entirely the same, so I doubt this patch is strictly necessary for a functional driver. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge CC state setup.Kenneth Graunke2011-05-175-1/+98
| | | | | | | | | The state itself still seems to be the same; the only change is that each part (CC, BLEND, DEPTH_STENCIL) can now be uploaded independently. Thus, we still rely on the code in gen6_cc.c to set up the state. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge WM/PS state setup.Kenneth Graunke2011-05-175-3/+322
| | | | | | | | | | Copied from gen6_wm_state.c. The main change from Sandybridge seems to be that 3DSTATE_WM was split into two separate state packet commands: 3DSTATE_WM and 3DSTATE_PS. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge SF/SBE state setup.Kenneth Graunke2011-05-175-2/+291
| | | | | | | | | | | | Copied from gen6_sf_state.c. The main change from Sandybridge seems to be that 3DSTATE_SF was split into two separate state packet commands: 3DSTATE_SF and 3DSTATE_SBE ("setup backend"). The bit-offsets are even the same - only the DWords numbers have shuffled around a bit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Make gen6_sf_state.c's get_attr_override non-static.Kenneth Graunke2011-05-172-1/+5
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initial Ivybridge URB space partitioning, including push constants.Kenneth Graunke2011-05-178-4/+162
| | | | | | | | | Currently this always reserves 16kB for push constants, regardless of how much space is needed, and partitions it evenly betwen the VS and FS. This is probably not ideal, but is straightforward. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Set maximum number of threads for Ivybridge.Kenneth Graunke2011-05-171-1/+11
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Split out tracked state atoms for Ivybridge.Kenneth Graunke2011-05-171-1/+70
| | | | | | | | Currently, gen7_atoms is a verbatim copy of gen6_atoms; future commits will update it to contain gen7-specific state. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Initial IS_GEN7 plumbing.Kenneth Graunke2011-05-173-3/+17
| | | | | | | | | Currently, IS_GEN7, IS_IVYBRIDGE, IS_IVB_GT1, and IS_IVB_GT2 all return false. This allows me to write the code for them before actually adding the PCI IDs and thus enabling the hardware. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename max_vs_handles to max_vs_entries for consistency.Kenneth Graunke2011-05-173-6/+6
| | | | | | | | | | | The documentation uses the term "vertex URB entries", the code talks about "entry size", and so on. Also, handles are just "pointers" to entries (actually small integers). Also rename max_gs_handles to max_gs_entries. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Convert BRW_NEW_* dirty bits to use an enum.Kenneth Graunke2011-05-171-21/+45
| | | | | | | | This will make it much easier to add new dirty bits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Rework IF/ELSE jump target back-patching.Kenneth Graunke2011-05-171-114/+144
| | | | | | | | | | | | | | | | | | | | | | | | | The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Move IF stack handling into the EU abstraction layer/brw_compile.Kenneth Graunke2011-05-1710-132/+122
| | | | | | | | This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Get a ralloc context into brw_compile.Kenneth Graunke2011-05-178-22/+44
| | | | | | | | | | | | This would be so much easier if we were using C++; we could simply use constructors and destructors. Instead, we have to update all the callers. While we're at it, ralloc various brw_wm_compile fields rather than explicitly calloc/free'ing them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gs: Move generation check for bailing earlier.Kenneth Graunke2011-05-171-6/+6
| | | | | | | | | On Sandybridge, we don't need to break down primitives. There's no need to bother setting up brw_compile and such if it's not going to be used; bail as early as possible. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add _NEW_LIGHT to Gen6 clip state dirty bits.Kenneth Graunke2011-05-171-1/+2
| | | | | | | | | ctx->Light.ProvokingVertex depends on _NEW_LIGHT. Found by inspection. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* r300/compiler: Fix bug in rc_get_variables()Tom Stellard2011-05-171-45/+13
| | | | | | | Variables that write to the same source select need to pe paired together otherwise the register allocator might fail. https://bugs.freedesktop.org/show_bug.cgi?id=36753
* i965: Pass brw_compile pointer to brw_set_src[01].Kenneth Graunke2011-05-163-98/+107
| | | | | | | | This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix "Paramater" typo in gen6_wm_state.c.Kenneth Graunke2011-05-161-1/+1
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* r300/compiler: Use ALU Result for IF conditionalsTom Stellard2011-05-146-20/+212
| | | | This saves one instruction per IF.
* i965: Use BRW_DATAPORT_READ_TARGET_DATA_CACHE instead of 0.Kenneth Graunke2011-05-131-3/+3
| | | | | | | | Using the #define'd constant is better than 0 with a comment. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Rename dp_render_target struct to gen6_dp.Kenneth Graunke2011-05-133-31/+31
| | | | | | | | | This is actually just the message descriptor for Gen6+ dataport access; it has nothing to do with the render cache. Access to the sampler cache and constant cache also would use this struct; rename for clarity. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Attempt to un-muddle Gen6 data port message target defines.Kenneth Graunke2011-05-132-6/+9
| | | | | | | | | | | | | | | | These are documented on page 245 of IHD_OS_Vol4_Part2.pdf (the public Sandybridge documentation/SEND instruction description). Somebody had the bright idea to reuse gen4/5 defines labelled READ/WRITE which just happened to be the same values as Render Cache/Sampler Cache. It turns out that this field has nothing to do with READ/WRITE on Sandybridge, but rather represents which data port to direct it to. This was especially confusing in brw_set_dp_read_message, which used "BRW_MESSAGE_TARGET_DATAPORT_WRITE." In a read function. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix incorrectly named data port define.Kenneth Graunke2011-05-131-1/+1
| | | | | | | According to my documentation this is actually "Media Block Write" on Gen4-5; there has never been a "DWord Block Write." Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Fix typo in Gen6 "DWord Scattered Write" message define.Kenneth Graunke2011-05-131-1/+1
| | | | | | It's DWORD, not DWORLD. Signed-off-by: Kenneth Graunke <[email protected]>
* r300/compiler: Fix bug in rc_get_variables()Tom Stellard2011-05-111-7/+11
| | | | | | Variables that share readers were not always being linked together. https://bugs.freedesktop.org/show_bug.cgi?id=36939
* r300/compiler: Limit instructions to 3 source selectsTom Stellard2011-05-114-39/+104
| | | | | | | | | Some presubtract conversions were generating more than 3 source selects. https://bugs.freedesktop.org/show_bug.cgi?id=36527 Note: This is a candidate for the 7.10 branch.
* r300/compiler: Add simple unit test frameworkTom Stellard2011-05-117-0/+579
| | | | Plus three tests for rc_inst_can_use_presub()
* r300/compiler: align memory allocations to 8-bytesMatt Turner2011-05-091-1/+1
| | | | | | | | | Eliminates unaligned accesses on strict architectures. Spotted by Jay Estabrook. Signed-off-by: Matt Turner <[email protected]> NOTE: This is a candidate for the 7.10 branch.
* r300c: Fix up for register allocator rewrite.Michel Dänzer2011-05-092-0/+2
| | | | | Was broken by commit fe622bac0c1b5b9f2a9fcf9f35b51232a06bea42 ('r300/compiler: Rewrite register allocator').
* r300/compiler: implement TXD and TXL opcodesMarek Olšák2011-05-075-0/+52
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* Add pci id for FirePro 2270Kostas Georgiou2011-05-062-0/+2
| | | | Signed-off-by: Kostas Georgiou <[email protected]>
* egl: Add a cursor use bit to MESA_drm_imageKristian Høgsberg2011-05-061-1/+9
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* r600c: add some new pci idsAlex Deucher2011-05-032-0/+8
| | | | Signed-off-by: Alex Deucher <[email protected]>
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