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* tnl: Push down the gl_vertex_array inputs into tnl drivers.Mathias Fröhlich2018-03-317-3/+27
| | | | | Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* i965: Push down the gl_vertex_array inputs into i965.Mathias Fröhlich2018-03-314-6/+23
| | | | | | | | | | Let the i965 backend have its own gl_vertex_array array and basically reimplement the way _vbo_draw works. Note that brw_draw_indirect_prims calls brw_draw_prims internally and gets its update to Array._DrawArray by this way. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* i965: Don't call process_glsl_ir() for SPIR-V shadersEduardo Lima Mitev2018-03-301-1/+2
| | | | | | | v2: Use 'spirv_data' from gl_linked_shader instead, to check if shader is SPIR-V. (Timothy Arceri) Reviewed-by: Timothy Arceri <[email protected]>
* i965: Call spirv_to_nir() instead of glsl_to_nir() for SPIR-V shadersEduardo Lima Mitev2018-03-301-2/+8
| | | | | | | | | | | This is the main fork of the shader compilation code-path, where a NIR shader is obtained by calling spirv_to_nir() or glsl_to_nir(), depending on its nature.. v2: Use 'spirv_data' member from gl_linked_shader to know which method to call. (Timothy Arceri) Reviewed-by: Timothy Arceri <[email protected]>
* i965: initialize SPIR-V capabilitiesAlejandro Piñeiro2018-03-301-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed for ARB_gl_spirv. Those are not the same that the Intel vulkan driver. From the ARB_spirv_extensions spec: "3. If a new GL extension is added that includes SPIR-V support via a new SPIR-V extension does it's SPIR-V extension also get enumerated by the SPIR_V_EXTENSIONS_ARB query?. RESOLVED. Yes. It's good to include it for consistency. Any SPIR-V functionality supported beyond the SPIR-V version that is required for the GL API version should be enumerated." So in addition to the core SPIR-V support, there is the possibility of specific GL extensions enabling specific SPIR-V extensions (so capabilities). That would mean that it is possible that OpenGL and Vulkan not having the same capabilities supported, even for the same driver. For this reason it is better to keep them separated. As an example: at the time of this patch writing Intel vulkan driver support multiview, but there isn't any OpenGL multiview GL extension supported. Note: we initialize SPIR-V capabilities at brwCreateContext instead of the usual brw_initialize_context_constants because we want to do that only if the extension is enabled. v2: * Rebase update (SpirVCapabilities not a pointer anymore) * Fill spirv capabilities for OpenGL >= 3.3 (Ian Romanick) v3: * Drop multiview support, as i965 doesn't support any multiview GL extension (Jason) * Fill spirv capabilities only if the extension is enabled (Jason) v4: Capabilities are supported only on gen7+. Added comment and assert (Jason)
* i965: Don't request GLSL IR lowering of gl_VertexIDIan Romanick2018-03-291-1/+0
| | | | | | | | | | | | | | | Let the lowering in NIR handle it instead. This hurts one shader that occurs twice in shader-db (SynMark GSCloth) on IVB and HSW. No other shaders or platforms were affected. total cycles in shared programs: 253438422 -> 253438426 (0.00%) cycles in affected programs: 412 -> 416 (0.97%) helped: 0 HURT: 2 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Antia Puentes <[email protected]>
* i965: Silence unused parameter warningIan Romanick2018-03-291-5/+3
| | | | | | | | | | src/mesa/drivers/dri/i965/brw_draw_upload.c: In function ‘double_types’: src/mesa/drivers/dri/i965/brw_draw_upload.c:225:34: warning: unused parameter ‘brw’ [-Wunused-parameter] double_types(struct brw_context *brw, ^~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* meson: use dep_libdrm version for pkg-configDylan Baker2018-03-291-1/+1
| | | | | | | | | This corrects pkg-config to use the libdrm version (as computed by the previous patch) instead of using a hardcoded value that may or may not (probably not) be right. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Drop unnecessary bo->align field.Kenneth Graunke2018-03-273-10/+0
| | | | | | | | bo->align is always 0; there's no need to waste 8 bytes storing it. Thanks to C99 initializers zeroing fields, we can completely drop the only read of the field altogether. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop unused alignment parameter from brw_bo_alloc().Kenneth Graunke2018-03-2714-26/+25
| | | | | | brw_bo_alloc no longer uses this parameter, so there's no point. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop alignment parameter from bo_alloc_internal().Kenneth Graunke2018-03-271-7/+6
| | | | | | | | | | | Buffers are always page aligned on 965+ hardware; I believe this extra parameter is a vestige from the Gen2-3 era. All callers pass 0, and in fact we assert that the alignment is 0 unless BO_ALLOC_BUSY is set (for some reason). We can just drop the parameter and set the value to 0 explicitly. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop BO_ALLOC_BUSY in intel_miptree_create_for_bo().Kenneth Graunke2018-03-271-2/+2
| | | | | | | intel_miptree_create_for_bo does not actually allocate a BO, so specifying allocation flags accomplishes nothing and is confusing. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop PIPE_CONTROL_NO_WRITE from various calls.Kenneth Graunke2018-03-274-11/+4
| | | | | | | This is just zero - passing nothing already gives us a post-sync operation of "nothing". Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: add performance query support on CNLLionel Landwerlin2018-03-224-1/+10415
| | | | | | | v2: Add brw_oa_cnl.xml to EXTRA_DIST (Emil) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: perf: add support for new equation operatorsLionel Landwerlin2018-03-221-0/+15
| | | | | | | | Some equations of the CNL metrics started to use operators we haven't defined yet, just add those. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: query topologyLionel Landwerlin2018-03-221-71/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introduction of asymmetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam to tell userspace what subslices are available. We introduce a new uAPI in the kernel driver to report exactly what part of the GPU are fused and require this to be available on Gen10+. Prior generations can continue to rely on GETPARAM on older kernels. This patch is quite a lot of code because we have to support lots of different kernel versions, ranging from not providing any information (for Haswell on 4.13 through 4.17), to being able to query through GETPARAM (for gen8/9 on 4.13 through 4.17), to finally requiring 4.17 for Gen10+. This change stores topology information in a unified way on brw_context.topology from the various kernel APIs. And then generates the appropriate values for the equations from that unified topology. v2: Move slice/subslice masks fields to gen_device_info (Rafael) v3: Add a gen_device_info_subslice_available() helper (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/perf: fix config registration when uploading to kernelLionel Landwerlin2018-03-221-1/+1
| | | | | | | | | | | | | | When registring configurations to the kernel for the first time, we run into an issue where the id number is not properly set (we're using the wrong variable). As a result when trying to use that id later on, we get an error. This issue manifest itself the first time you use frameretrace after reboot, subsequent runs are fine. Fixes: 27ee83eaf7e9 ("i965: perf: add support for userspace configurations") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Disable fast color clear on iclAnuj Phogat2018-03-221-0/+5
| | | | | | | | | Disabling fast color clear makes fbo-clearmipmap test render correct texture in base miplevel. Fast color clear is anyways disabled for non-base miplevels. Acked-by: Matt Turner <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: fix android buildLionel Landwerlin2018-03-211-2/+5
| | | | | | | | | | | | | This is the equivalent of commit 5770e1d89e0eb49eb3c9547e8657d636b6e7e5d7 for android. v2: fix xml files path and file given to --header Signed-off-by: Lionel Landwerlin <[email protected]> Signed-off-by: Tapani Pälli <[email protected]> Fixes: 2d2b15fbcab ("i965: fix autotools/android build") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105634 Reviewed-by: Emil Velikov <[email protected]>
* intel/blorp: Fix compiler warning about num_layers.Eric Anholt2018-03-201-1/+1
| | | | | | | | | | The compiler doesn't notice that the condition for num_layers to be undefined already defined it above (as our assert checked in a debug build). v2: Move the pair of assignments to one outside of the block. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: fix out of tree autotools buildLionel Landwerlin2018-03-201-1/+4
| | | | | | | Fixes: 2d2b15fbcab ("i965: fix autotools/android build") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Mathias Fröhlich <[email protected]>
* i965: annotate brw_oa.py's --header and --code as requiredEmil Velikov2018-03-201-21/+14
| | | | | | | | | | | | As of earlier commit, the --header was made a hard requirement when using --code. Hence - annotate both as required and drop a few no longer needed checks. Fixes: 035cc7a12dc0 ("i965: perf: reduce i965 binary size") Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: pipecontrol: add LRI write immediate flagLionel Landwerlin2018-03-201-0/+1
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: fix autotools/android buildLionel Landwerlin2018-03-202-13/+6
| | | | | | | | | | | | | Autotools/android builds generate the header & code files in 2 steps, but the code generation requires the name of the header file to include it. This change generates both files in one command. Fixes: 035cc7a12dc ("i965: perf: reduce i965 binary size") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: perf: reduce i965 binary sizeLionel Landwerlin2018-03-206-221/+334
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Performance metric numbers are calculated the following way : - out of the 256 bytes long OA reports, we accumulate the deltas into an array of uint64_t - the equations' generated code reads the accumulated uint64_t deltas and normalizes them for a particular platform Our hardware is such that a number of counters in the OA reports always return the same values (i.e. they're not programmable), and they return the same values even across generations, and as a result a number of equations are identical in different metric sets across different generations. Up to now we've kept the generated code of the equations separated in different files (per generation/GT), and didn't apply any factorization of the common equations. We could have make some improvement by reusing equations within a given metrics file, but we can go even further and reuse across generations (i.e. all files). This change changes the code generation to emit a single file in which we reuse equations emitted code based on the hash of equations' strings. Here are the savings in a meson build : Before(.old)/after : $ du -h ./build/src/mesa/drivers/dri/libmesa_dri_drivers.so ./build/src/mesa/drivers/dri/libmesa_dri_drivers.so.old 43M ./build/src/mesa/drivers/dri/libmesa_dri_drivers.so 47M ./build/src/mesa/drivers/dri/libmesa_dri_drivers.so.old $ size build/src/mesa/drivers/dri/libmesa_dri_drivers.so build/src/mesa/drivers/dri/libmesa_dri_drivers.so.old text data bss dec hex filename 13054002 409424 671856 14135282 d7aff2 build/src/mesa/drivers/dri/libmesa_dri_drivers.so 14550386 409552 671856 15631794 ee85b2 build/src/mesa/drivers/dri/libmesa_dri_drivers.so.old As a side comment here is the size of the drivers if we remove all of the metrics from the build : $ du -sh build/src/mesa/drivers/dri/libmesa_dri_drivers.so 40M build/src/mesa/drivers/dri/libmesa_dri_drivers.so v2: Fix an issue with hashing of counter equations (Lionel) Build system rework (Emil) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (build system part) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: fix a counter return type on hswLionel Landwerlin2018-03-201-1/+1
| | | | | | | | The equation code computes a float (percentage) yet the return type was an uint64_t. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* st/nir: fix atomic lowering for gallium driversTimothy Arceri2018-03-201-1/+1
| | | | | | | | | | | | | | | i965 and gallium handle the atomic buffer index differently. It was just by luck that the single piglit test for this was passing. For gallium we use the atomic binding so that we match the handling in st_bind_atomics(). On radeonsi this fixes the CTS test: KHR-GL43.shader_storage_buffer_object.advanced-write-fragment It also fixes tressfx hair rendering in Tomb Raider. Reviewed-by: Marek Olšák <[email protected]>
* mesa: rework ParameterList to allow packingTimothy Arceri2018-03-203-9/+13
| | | | | | | | | | | | | | Currently everything is padded to 4 components. Making the list more flexible will allow us to do uniform packing. V2 (suggestions from Nicolai): - always pass existing calls to _mesa_add_parameter() true for padd_and_align - fix bindless param value offsets - remove left over wip logic from pad and align code - zero out param value padding - whitespace fix Reviewed-by: Marek Olšák <[email protected]>
* i965: Allow disk shader cache usage with LINKING_SUCCESS statusJordan Justen2018-03-191-3/+0
| | | | | | | | | | | | | | | | | | | | Currently, we only look in the disk shader cache if we see that the shader program is in the cache during the link step. If the shader cache entry isn't found during the program link, there are still some (fairly unlikely) scenarios where later it might be useful to search the cache for gen binary programs. 1. If the cache evicts the serialized glsl cache, there might still be valid gen program entries in the disk cache. 2. If two applications are running in parallel, then it is possible that one may write out the cached gen program item which the other application can then make use of. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Allow disk shader cache usage with transform feedbackJordan Justen2018-03-191-8/+0
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105444 Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add INTEL_DEBUG stages support for disk shader cacheJordan Justen2018-03-191-0/+26
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: silence unused function warningLionel Landwerlin2018-03-151-1/+1
| | | | | | | | | | [123/227] Compiling C object 'src/mesa/drivers/dri/i965/libi965_gen110@sta/genX_blorp_exec.c.o'. ../src/mesa/drivers/dri/i965/genX_blorp_exec.c:99:1: warning: ‘blorp_get_surface_base_address’ defined but not used [-Wunused-function] blorp_get_surface_base_address(struct blorp_batch *batch) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* i965: Emit texture cache invalidates around blorp_copyJason Ekstrand2018-03-131-0/+15
| | | | | | | | | | | This is a terrible hack but it fixes CTS regressions. It's still incredibly unclear exactly what is going wrong in the hardware to cause this to be an issue so this isn't a good fix by any means. However, it does fix tests so there is that. Fixes: fb0e9b5197 "i965: Track the depth and render caches separately" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103746 Acked-by: Kenneth Graunke <[email protected]>
* mesa: Make gl_vertex_array contain pointers to first order VAO members.Mathias Fröhlich2018-03-105-115/+149
| | | | | | | | | | | | | | | Instead of keeping a copy of the vertex array content in struct gl_vertex_array only keep pointers to the first order information originaly in the VAO. For that represent the current values by struct gl_array_attributes and struct gl_vertex_buffer_binding. v2: Change comments. Remove gl... prefix from variables except in the i965 directory where it was like that before. Reindent because of that. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* i965: Hard code CS scratch_ids_per_subslice for CherryviewJordan Justen2018-03-091-17/+27
| | | | | | | | | | | | | Ken suggested that we might be underallocating scratch space on HD 400. Allocating scratch space as though there was actually 8 EUs seems to help with a GPU hang seen on synmark CSDof. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104636 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105290 Cc: <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Eero Tamminen <[email protected]>
* i965: perf: consolidate unmapping oa perf bo outside accumulationLionel Landwerlin2018-03-081-4/+3
| | | | | | | | | Do this in one place outside the only caller of the accumulation function. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: count number of accumlated reportsLionel Landwerlin2018-03-081-0/+6
| | | | | | | | This will be reused later. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: reuse timescale base function from queryLionel Landwerlin2018-03-081-11/+2
| | | | | | | | We already have the same function in brw_queryobj.c Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: store sysfs device entry into contextLionel Landwerlin2018-03-082-76/+73
| | | | | | | | We want to reuse it later on. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: store the hw_id of the context in the queryLionel Landwerlin2018-03-081-6/+11
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: default case for unknown query typesLionel Landwerlin2018-03-081-1/+31
| | | | | | | | Just some extra safety before further changes. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Add missing includes for building on AndroidClayton Craft2018-03-061-0/+1
| | | | | | | | | | | This adds a missing library to the i965/Android.mk file, and updates intel/Android.mk to include the new library. Without this, mesa does not build on Android. Fixes: 272bef0601a "intel: Split gen_device_info out into libintel_dev" Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-051-4/+4
| | | | | | | | | | | We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <[email protected]> [[email protected]: Minor changes for rebase] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-055-4/+6
| | | | | | | | | | | | Split out the device info so isl doesn't depend on intel/common. Now it will depend on the new intel/dev device info lib. This will allow the decoder in intel/common to use isl, allowing us to apply Ken's patch that removes the genxml duplication of surface formats. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Silence unused parameter warnings in genX_state_uploadIan Romanick2018-03-021-20/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduces my build from 1772 warnings to 1717 warnings by silencing 55 instances of things like ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘gen4_emit_vertex_buffer_state’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:313:41: warning: unused parameter ‘end_offset’ [-Wunused-parameter] unsigned end_offset, ^~~~~~~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘gen4_emit_sampler_state_pointers_xs’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4689:58: warning: unused parameter ‘brw’ [-Wunused-parameter] genX(emit_sampler_state_pointers_xs)(struct brw_context *brw, ^~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4690:62: warning: unused parameter ‘stage_state’ [-Wunused-parameter] struct brw_stage_state *stage_state) ^~~~~~~~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘gen4_upload_default_color’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4730:40: warning: unused parameter ‘format’ [-Wunused-parameter] mesa_format format, GLenum base_format, ^~~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘translate_wrap_mode’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4906:41: warning: unused parameter ‘brw’ [-Wunused-parameter] translate_wrap_mode(struct brw_context *brw, GLenum wrap, bool using_nearest) ^~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘gen4_update_sampler_state’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4972:37: warning: unused parameter ‘batch_offset_for_sampler_state’ [-Wunused-parameter] uint32_t batch_offset_for_sampler_state) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Silence unused parameter warnings in blorpIan Romanick2018-03-022-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduces my build from 2023 warnings to 1960 warnings by silencing 63 instances of things like In file included from ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:33:0: ../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h: In function ‘blorp_emit_cc_viewport’: ../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h:500:51: warning: unused parameter ‘params’ [-Wunused-parameter] const struct blorp_params *params) ^~~~~~ ../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h: In function ‘blorp_emit_sampler_state’: ../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h:524:53: warning: unused parameter ‘params’ [-Wunused-parameter] const struct blorp_params *params) ^~~~~~ In file included from ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:36:0: ../../SOURCE/master/src/mesa/drivers/dri/i965/gen4_blorp_exec.h: In function ‘blorp_emit_vs_state’: ../../SOURCE/master/src/mesa/drivers/dri/i965/gen4_blorp_exec.h:50:48: warning: unused parameter ‘params’ [-Wunused-parameter] const struct blorp_params *params) ^~~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c: In function ‘blorp_flush_range’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:39: warning: unused parameter ‘batch’ [-Wunused-parameter] blorp_flush_range(struct blorp_batch *batch, void *start, size_t size) ^~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:52: warning: unused parameter ‘start’ [-Wunused-parameter] blorp_flush_range(struct blorp_batch *batch, void *start, size_t size) ^~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:66: warning: unused parameter ‘size’ [-Wunused-parameter] blorp_flush_range(struct blorp_batch *batch, void *start, size_t size) ^~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Silence unused parameter warnings in generated OA codeIan Romanick2018-03-021-1/+1
| | | | | | | | | | | | | | Reduces my build from 6301 warnings to 2075 warnings by silencing 4226 instances of things like src/mesa/drivers/dri/i965/i965@sta/brw_oa_hsw.c: In function ‘hsw__render_basic__gpu_core_clocks__read’: src/mesa/drivers/dri/i965/i965@sta/brw_oa_hsw.c:41:62: warning: unused parameter ‘brw’ [-Wunused-parameter] hsw__render_basic__gpu_core_clocks__read(struct brw_context *brw, ^~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Silence unused parameter warningsIan Romanick2018-03-021-1/+1
| | | | | | | | | | | | | | | Reduces my build from 7119 warnings to 7005 warnings by silencing 114 instances of In file included from ../../SOURCE/master/src/mesa/drivers/dri/i965/brw_context.h:46:0, from ../../SOURCE/master/src/mesa/drivers/dri/i965/intel_pixel_read.c:38: ../../SOURCE/master/src/mesa/drivers/dri/i965/brw_bufmgr.h: In function ‘brw_bo_unmap’: ../../SOURCE/master/src/mesa/drivers/dri/i965/brw_bufmgr.h:258:47: warning: unused parameter ‘bo’ [-Wunused-parameter] static inline int brw_bo_unmap(struct brw_bo *bo) { return 0; } ^~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Mark upload buffers with MAP_ASYNC and MAP_PERSISTENT.Kenneth Graunke2018-03-021-1/+3
| | | | | | | | | This should have no practical impact. For the default uploader, we don't really care, but for others, we may want to append more data as the GPU is reading existing data, which means we need async and persistent flags. Reviewed-by: Chris Wilson <[email protected]>
* i965: Generalize intel_upload.c to support multiple uploaders.Kenneth Graunke2018-03-029-91/+101
| | | | | | | | | | | | | I'd like to reuse the upload logic for a new program cache, but the buffers will need to have a different lifetime than the default uploader, and also some address space restrictions. So, we can't use a single uploader for both situations - we'll need two of them. This creates a public 'uploader' structure, and adjusts the interface to take an uploader rather than always using brw->upload. It should have no functional change at the moment. Reviewed-by: Chris Wilson <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 02:23:37 +0000