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* i965/miptree: Use num_samples of 1 instead of 0 for single-sampledTopi Pohjolainen2017-07-2010-32/+38
| | | | | | | | | | | | | | | | | | | | | Patch moves "assert(brw->num_samples <= 16)" from emit_3dstate_multisample2() to upload_multisample_state(). Latter is the only caller of the former and passes "brw->num_samples" as argument. Therefore it is clearer to assert in the caller. Possible bug fix in genX(emit_3dstate_multisample2) which doesn't have a case for num_samples == 0 in the switch statement. It should be noted that intel_miptree_map()/unmap() now checks additionally for "mt->surf.samples == 1" in order to support gen6 stencil which is already transitioned to ISL. This will go away in next patch when native miptrees start to use isl_surf::samples as well. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Switch to isl_surf::msaa_layoutTopi Pohjolainen2017-07-206-131/+30
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* drirc: whitelist War Thunder (Wine) for glthreadMarek Olšák2017-07-191-0/+3
| | | | Nominated by František Zatloukal <[email protected]>
* dri/common: use designated initializers for OptConfElemsEmil Velikov2017-07-191-1/+4
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* swrast: add dri2ConfigQueryExtension to the correct extension listEmil Velikov2017-07-191-1/+0
| | | | | | | | | | | | The extension should be in the list as returned by getExtensions(). Seems to have gone unnoticed since close to nobody wants to change the vblank mode for the software driver. v2: Rebase Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (v1)
* radeon: remove local vblank_mode optionEmil Velikov2017-07-191-2/+0
| | | | | | | Analogous to previous commits. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* i915: remove local vblank_mode optionEmil Velikov2017-07-191-1/+0
| | | | | | | Analogous to previous commit. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* i965: remove local vblank_mode optionEmil Velikov2017-07-191-1/+0
| | | | | | | | | | | The option is only queried from the loader, which has access to the dri common code in src/mesa/drivers/dri/common/. One could grant the loader access to brw_config_options but even then, having the same option in both places is not a good idea. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* i965/blorp: Use the return value of brw_emit_reloc.Kenneth Graunke2017-07-181-3/+3
| | | | | | | This guarantees that the value written in the batch matches the value recorded in the relocation entry. (Chris Wilson wrote an identical patch as well.)
* i965: Delete dead brw_program_reloc function.Kenneth Graunke2017-07-181-15/+0
| | | | Rafael eliminated the last use of brw_program_reloc recently.
* i965: Convert WM_STATE to genxml on gen4-5.Rafael Antognolli2017-07-186-437/+153
| | | | | | | | | | | | | The code doesn't get exactly a lot simpler but at least it is in a single place, and we delete more than we add. Another good point is that you get rid of struct brw_wm_unit_state which was a third mechanism for encoding GEN state. We used to have GENXML, manual packing and these bitfield structs. Now we're down to just GENXML and some manual packing. (Khristian) Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Convert CLIP_STATE to genxml.Rafael Antognolli2017-07-184-215/+100
| | | | | | | | | | | Add the code into its own function and atom, since almost nothing is shared with GEN >= 6. v2: Split GEN <=5 and GEN >= 6 into separate functions (Ken). v3: Minor tidying by Ken. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4: Set tile offsets to zero after depth rebaseTopi Pohjolainen2017-07-181-4/+6
| | | | | | | | | | | | | | | | | | | | Current logic calls intel_renderbuffer_set_draw_offset() which in turn tries to calculate x and y offset against layer/level settings that are against the original miptree actually having sufficient levels/layers. This returns correctly x=0 y=0 regardless of the given layer/level only because one calls intel_miptree_get_image_offset() which goes and consults miptree offset table which in turn luckily contains entries for max-mipmap levels, all initialised to zero even in case of non-mipmapped. This patch stops consulting the table and simply sets the draw offsets to zero that are compatible with the single slice miptree backing the renderbuffer. This prepares for ISL based miptrees that calculate offsets on-demand and do not tolerate levels beyond what the miptree has. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Refactor check for separate stencilTopi Pohjolainen2017-07-181-4/+20
| | | | | | | v2 (Jason): s/needs_stencil/needs_separate_stencil/ Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/wm: Use level offsets directlyTopi Pohjolainen2017-07-181-2/+2
| | | | | | | dropping dependency to slice table. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Use offset helper in intel_readpixels_tiled_memcpy()Topi Pohjolainen2017-07-181-2/+5
| | | | | | | providing support for isl based. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Pass flags instead of explicit tiling to surface creatorTopi Pohjolainen2017-07-181-5/+8
| | | | | | | allowing one to use isl tiling filter. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Add pitch override for imported buffer objectsTopi Pohjolainen2017-07-181-3/+4
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Stop setting total_width/height for existing boTopi Pohjolainen2017-07-182-6/+0
| | | | | | | | | | Now that image surface vertical slice calculator doesn't depend on total_height, total dimensions are only needed when new buffer objects are created. Therefore one can safely ignore them when miptrees are created for already exisiting buffer objects. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/wm: Use isl for filling tex image parametersTopi Pohjolainen2017-07-183-92/+19
| | | | | | | | This helps to drop dependency to miptree::total_height which is used in brw_miptree_get_vertical_slice_pitch(). Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Check for miptree_create() failuresTopi Pohjolainen2017-07-181-0/+2
| | | | | | | Rest of the function assumes it always succeeds. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Do not rely on msaa type to decide if aux is neededTopi Pohjolainen2017-07-182-4/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Once the driver moves to ISL both compressed and uncompressed have the same type. One needs to tell them apart by other means. This can be done by checking the existence of mcs_buf. There is a short period of time within intel_miptree_create() where mcs_buf doesn't exist yet (between calls to intel_miptree_create_layout() and intel_miptree_alloc_mcs()). First compute_msaa_layout() makes the decision if compression is to be used and sets the msaa_layout type. Then based on the type one sets aux_usage and finally decides if mcs_buf is needed. This patch duplicates the logic in compute_msaa_layout() and uses that to make the decision on aux_usage and mcs_buf allocation. Most of the original logic in compute_msaa_layout() will be gone in later patch leaving only one version. Elsewhere only brw_populate_sampler_prog_key_data() needs to know if compression is used based on the msaa_type. This is now replaced with consideration for number of samples and existence of mcs_buf. All other occurrences consider CMS || UMS which can be represented using single the type of ISL_MSAA_LAYOUT_ARRAY without any tweaks. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Make irb::mt_layer logical instead of physicalTopi Pohjolainen2017-07-184-59/+12
| | | | | | | | | same as irb::layer_count. In case of copies and blits msaa surfacas already fall to blorp which natively works with logical slices. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/tex: Use offset helper instead of accessing table directlyTopi Pohjolainen2017-07-182-4/+8
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Mark read-only args as const in intel_miptree_supports_hiz()Topi Pohjolainen2017-07-181-2/+2
| | | | | | Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Use > 1 instead of > 0 to check for multisamplingTopi Pohjolainen2017-07-181-2/+2
| | | | | | | | | | | | Checking against zero currently works as single sampling is represented with zero. Once one moves to isl single sampling really has sample number of one. This keeps later patches simpler. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Set refcount before failing via _release()Topi Pohjolainen2017-07-181-1/+2
| | | | | | | | | Otherwise one wraps uint to UINT_MAX via -1. Fixes: 3cf470f2b6c ("i965: Add isl based miptree creator") Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Delete brw_sf_state.c againKenneth Graunke2017-07-171-200/+0
| | | | | | | | | | | | "...and stay dead!" Rafael deleted this file in c2b5a26dc25b9c62954a75465e25294c7fd3851a (i965: Convert SF_STATE to genxml.) but Marek accidentally brought it back in commit e7a091936fb6fd578c6ced9baa38b306b638a11b (mesa: replace ctx->Polygon._FrontBit with a helper function) when resolving conflicts. It's not actually even compiled, but it's still here trolling people into thinking it still exists and needs patching.
* i965: Check if the modifier is supported in select_best_modifierJason Ekstrand2017-07-171-0/+3
| | | | | | | | Otherwise, if a client gave us a list of modifiers that contained a modifier we understand but which is not supported on the hardware, we might return that one and then fail to create the image. Reviewed-by: Daniel Stone <[email protected]>
* i965: Rework the modifier info mapJason Ekstrand2017-07-171-23/+25
| | | | | | | | | | This commit splits the mapping in half. The modifier_infos table now only contains the modifier and the since_gen field. The tiling bits have been moved into a table in tiling_to_modifier as that's the only place it was ever used. The modifier_is_supported function now takes a devinfo and does the since_gen check. Reviewed-by: Daniel Stone <[email protected]>
* i965/surface_state: Remove the mcs_buf->offset == 0 restrictionJason Ekstrand2017-07-171-1/+0
| | | | | | | | | This assert was removed in b0cc55f29831638069407a4c1a5c809b26902ab6 but got added back in 1a43d774b613d0b00e26b28cc752d944ce8049aa, probably by accident. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/isl: Add a row_pitch parameter to surf_get_ccs_surfJason Ekstrand2017-07-171-1/+2
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Use BO_ALLOC_ZEROED for CCS_E buffersJason Ekstrand2017-07-171-23/+13
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/screen: Allocate ZEROED BOs for imagesJason Ekstrand2017-07-171-1/+5
| | | | Reviewed-by: Chad Versace <[email protected]>
* i965/bufmgr: Add a BO_ALLOC_ZEROED flagJason Ekstrand2017-07-172-2/+27
| | | | | Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/miptree: Replace is_lossless_compressed with mt->aux_usage checksJason Ekstrand2017-07-175-41/+10
| | | | | | | | | | Now that we have an actual aux_usage field, we no longer need the complex logic of is_lossless_compressed in order to figure out if a miptree is CCS_E compressed. As a side-effect, there is not longer any need to overload MSAA_LAYOUT_CMS for CCS_E and we can stop doing so. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Allocate HiZ up-frontJason Ekstrand2017-07-172-17/+6
| | | | | | | | | | | | | HiZ, like MCS and CCS_E, can compress more than just clear colors so we want it turned on whenever the miptree is being used as a depth attachment. It's theoretically possible for someone to create a depth texture, upload data with glTexSubImage2D, and texture from it without ever binding it as a depth target. If this happens, we would end up wasting a bit of space by allocating a HiZ surface we never use. However, this is rather unlikely out side of test cases, so we're better off just allocating it up-front. Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Add an intel_tiling_supports_hiz helperJason Ekstrand2017-07-171-1/+11
| | | | | | | | | | We need this split for the same reason that we need the split for CCS: intel_miptree_supports_hiz is called *before* we choose the actual tiling. Adding a tiling_supports_hiz helper lets choose_aux_usage more accurately decide whether or not to enable hiz. In particular, this prevents us from enabling HiZ on linear depth buffers. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Gather initial aux allocation into a single functionJason Ekstrand2017-07-171-30/+53
| | | | | Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: use strtol to convert the integer deviceID overrideEmil Velikov2017-07-171-1/+1
| | | | | | | | | | | | | | | | One can override the deviceID, by setting the INTEL_DEVID_OVERRIDE variable. A few symbolic names or a numerical value for the actual device ID is accepted. At the same time we're using strtod (string to double) to convert the string to a decimal numeral. A seeming thinko, made by the original commit that introduces the code in libdrm_intel and got here with the import. Fixes: 514db96c117a ("i965: Import libdrm_intel.") Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: miptree: silence coverity warningLionel Landwerlin2017-07-171-1/+1
| | | | | | | | | | This probably can't happen, but we're better off with initialized variables. CID: 1415114 Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* dri: Make classic drivers allow __DRI_CTX_FLAG_NO_ERROR.Kenneth Graunke2017-07-175-6/+7
| | | | | | | | | | | | | Grigori recently added EGL_KHR_create_context_no_error support, which causes EGL to pass a new __DRI_CTX_FLAG_NO_ERROR flag to drivers when requesting an appropriate context mode. driContextSetFlags() will already handle it properly for us, but the classic drivers all have code to explicitly balk at unknown flags. We need to let it through or they'll fail to create a no_error context. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Grigori Goronzy <[email protected]>
* i965: Compile with -msse2 (instead of -msse2)Matt Turner2017-07-141-1/+1
| | | | | Ian noted that were were two Pentium 4 Extreme Edition LGA 775 CPUs, and they only have SSE2.
* i965: Compile with -msse3Matt Turner2017-07-141-1/+2
| | | | | | | | | | | | All CPUs that can be paired with a GPU supported by i965_dri.so supports SSE3. This allows us to ensure that some vectorized version of the tiled memcpy path is enabled on 32-bit systems. This also ensures that __builtin_ia32_clflush is always usable. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101774 Tested-by: Tobias Klausmann <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* drirc: whitelist glthread for Euro Truck Simulator 2Petr Sebor2017-07-141-0/+3
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* drirc: whitelist glthread for American Truck SimulatorPetr Sebor2017-07-141-0/+3
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* drirc: whitelist glthread for The Witcher 2Edmondo Tommasina2017-07-141-0/+3
| | | | | | | | Performance delta on AMD Phenom II X3 720 / RX 470 The Witcher 2: +18% Signed-off-by: Marek Olšák <[email protected]>
* drirc: whitelist glthread for Civilization 5Edmondo Tommasina2017-07-141-0/+3
| | | | | | | | Performance delta on AMD Phenom II X3 720 Civilization 5: +28% Signed-off-by: Marek Olšák <[email protected]>
* st/mesa: Add KHR_no_error toggle to driconfGrigori Goronzy2017-07-141-0/+5
| | | | | | | | Allows applications to be whitelisted. v2: Remove misguided DRI common part. Reviewed-by: Marek Olšák <[email protected]>
* dri: Add KHR_no_error DRI extensionGrigori Goronzy2017-07-147-2/+18
| | | | | | | | | | This basic extension allows usage of the __DRI_CTX_FLAG_NO_ERROR flag. This includes support code for classic Mesa drivers to switch on the no-error mode if the flag is set. v2: Move to common DRI code. Reviewed-by: Marek Olšák <[email protected]>
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