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* i965/eu: Add a devinfo parameter to brw_compileJason Ekstrand2015-04-222-0/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Do better fake context setup in unit testsJason Ekstrand2015-04-225-5/+24
| | | | | | | In future tests, we will start relying on devinfo and not just brw in the compiler. Changing this now keeps these tests from failing in the future. Reviewed-by: Matt Turner <[email protected]>
* i965: Remove the context parameter from brw_texture_offsetJason Ekstrand2015-04-225-12/+5
| | | | | | | | It wasn't really being used anyway. We used it to assert that gpu_shader5 is supported in the back-end but that should be caught by the front-end. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* android: xmlpool: cleanup the generation rulesEmil Velikov2015-04-221-3/+2
| | | | | | | | | - Do not attempt to create the save folder twice - both dir $@ and PRIVATE_LOCALEDIR point to the same place. - Use @ and $(hide), for mkdir and python, to avoid spamming the output. Signed-off-by: Emil Velikov <[email protected]>
* android: xmlpool: Get rid of the last use of intermediates-dir-forChih-Wei Huang2015-04-222-10/+7
| | | | | | | | | v2 [Emil Velikov] - Keep the PRIVATE_LOCALEDIR variable. - Do not use $(@D) but the more widespead $(dir $@) Signed-off-by: Chih-Wei Huang <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* android: export the path of the generated headersChih-Wei Huang2015-04-222-1/+2
| | | | | | | The modules need the headers can get the path automatically. Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* android: fix the building rules for Android 5.0Chih-Wei Huang2015-04-223-2/+9
| | | | | | | | | | | | | | | | | Android 5.0 allows modules to generate source into $OUT/gen, which will then be copied into $OUT/obj and $OUT/obj_$(TARGET_2ND_ARCH) as necessary. Modules will need to change calls to local-intermediates-dir into local-generated-sources-dir. The patch changes local-intermediates-dir into local-generated-sources-dir. If the Android version is less than 5.0, fallback to local-intermediates-dir. The patch also fixes the 64-bit building issue of Android 5.0. v2 [Emil Velikov] - Keep the LOCAL_UNSTRIPPED_PATH variable. Signed-off-by: Chih-Wei Huang <[email protected]>
* android: dri: link against libmesa_utilEmil Velikov2015-04-221-1/+2
| | | | | | | | The dri modules depend on symbols provided by it. Cc: "10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: add gallium dirs to more places in the treeEmil Velikov2015-04-221-0/+2
| | | | | | | | Similar to e8c5cbfd921(mesa: Add gallium include dirs to more parts of the tree.) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: dri/common: conditionally include drm_cflags/set __NOT_HAVE_DRM_HEmil Velikov2015-04-221-0/+14
| | | | | | | Otherwise we'll fail to find the drm.h header. Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* android: add $(mesa_top)/src include to the whole of mesaEmil Velikov2015-04-221-1/+0
| | | | | | | | | Many parts of mesa already have the include with others depending on it but it's missing. Add it once at the top makefile and be done with it. Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* android: use LOCAL_SHARED_LIBRARIES over TARGET_OUT_HEADERSEmil Velikov2015-04-221-1/+0
| | | | | | | | | ... to manage the LIBDRM*_CFLAGS. The former is the recommended approach by the Android build system developers while the latter has been depreciated for quite some time. Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* drirc: Add "Second Life" quirk (allow_glsl_extension_directive_midshader).Kenneth Graunke2015-04-211-0/+4
| | | | | | | | | | | | Appears to fix shader compilation. Tested by starting the client, dragging the "quality and speed" slider back and forth, and watching the console output - instead of piles of "shader failed to compile", the CPU seems to be busy compiling shaders. I haven't actually tried to play. Signed-off-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69226 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71591 Cc: [email protected]
* i965/fs: Combine pixel center calculation into one inst.Matt Turner2015-04-213-20/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | The X and Y values come interleaved in g1 (.4-.11 inclusive), so we can calculate them together with a single add(32) instruction on some platforms like Broadwell and newer or in SIMD8 elsewhere. Note that I also moved the PIXEL_X/PIXEL_Y virtual opcodes from before LINTERP to after it. That's because the writes_accumulator_implicitly() function in backend_instruction tests for <= LINTERP for determining whether the instruction indeed writes the accumulator implicitly. The old FS_OPCODE_PIXEL_X/Y emitted ADD instructions, which did, but the new opcodes just emit MOVs, which don't. It doesn't matter, since we don't use these opcodes on Gen4/5 anymore, but in the case that we do... On Broadwell: total instructions in shared programs: 7192355 -> 7186224 (-0.09%) instructions in affected programs: 1190700 -> 1184569 (-0.51%) helped: 6131 On Haswell: total instructions in shared programs: 6155979 -> 6152800 (-0.05%) instructions in affected programs: 652362 -> 649183 (-0.49%) helped: 3179 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Calculate delta_x and delta_y together.Matt Turner2015-04-217-74/+79
| | | | | | | | | | | | | This lets SIMD16 programs on G45 and Gen5 use the PLN instruction. On Ironlake: total instructions in shared programs: 5634757 -> 5518055 (-2.07%) instructions in affected programs: 1745837 -> 1629135 (-6.68%) helped: 11439 HURT: 4 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.Matt Turner2015-04-215-51/+8
| | | | | | | | | | These were used only on Gen4 and 5. emit_interpolation_setup_gen6() emits ADDs directly. The virtual opcodes weren't providing anything useful. I'm going to repurpose these opcodes, so deleting and readding them makes it simpler to see what's going on. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Manually set source regioning on PLN instructions.Matt Turner2015-04-211-1/+13
| | | | | | | | Like LINE (commit 92346db0), src0 must have a scalar region. Setting src1's region to <8,8,1> lets us pass a properly sized combined delta_xy argument in a few commits without getting a bogus <16,16,1> region. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Add LINTERP's src0 to fs_inst::regs_read().Matt Turner2015-04-211-11/+2
| | | | | | | | | | LINTERP's src0 is PLN's src1, and PLN's src1 reads exec_size / 4 registers. Having that information lets us drop the delta_x/y special case code in split_virtual_grfs(). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Set compression only if writing two registers.Matt Turner2015-04-211-1/+4
| | | | | | | We don't want to set compression control on a SIMD16 instruction operating on words or smaller. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Allow an execution size of 32.Matt Turner2015-04-212-1/+2
| | | | | | | In a few commits, we'll start emitting an add(32) instruction on some platforms. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make type_sz() return unsigned.Matt Turner2015-04-211-1/+1
| | | | | | Avoids annoying warnings when comparing with sizeof(...). Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Replace guess_execution_size with something simpler.Matt Turner2015-04-214-27/+35
| | | | | | | | | | | | | | | | | | | | | | | guess_execution_size() does two things: 1. Cope with small destination registers. 2. Cope with SIMD8 vs SIMD16 mode. This patch replaces the first with a simple if block in brw_set_dest: if the destination register width is less than 8, you probably want the execution size to match. (I didn't put this in the 3src block because it doesn't seem to matter.) Since only the FS compiler cares about SIMD16 mode, it's easy to just set the default execution size there. This pattern was already been proven in the Gen8+ generator, but we didn't port it back to the existing generator when we combined the two. This is based on a patch from Ken from about a year ago. I've rebased it and and fixed a few bugs. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.Matt Turner2015-04-212-3/+3
| | | | | | The BSpec says this applies to Gen6 as well. Reviewed-by: Jason Ekstrand <[email protected]>
* radeon: replace __FUNCTION__ with __func__Marius Predut2015-04-2132-116/+116
| | | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Signed-off-by: Marius Predut <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965/skl: Fix the qpitch valueNeil Roberts2015-04-202-13/+59
| | | | | | | | | | | | | | | | | | On Skylake the qpitch value is uploaded as part of the surface state so we don't need to add the extra rows that are done for other generations. However for 3D textures it needs to be aligned to the tile height and for depth/stencil textures it needs to be a multiple of 8. Unlike previous generations the qpitch is measured as a multiple of the block size for compressed surfaces. When the horizontal mipmap layout is used for 1D textures then the qpitch is measured in pixels instead of rows. v2: Align the depth/stencil textures to a multiple of 8 v3: Add an assert that ALL_SLICES_AT_EACH_LOD is not used. Ignore the vertical alignment when picking the qpitch for 1D_ARRAY textures. Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Don't use ALL_SLICES_AT_EACH_LODNeil Roberts2015-04-201-10/+20
| | | | | | | | | | | | | | | | | | | | | The render surface state command for Skylake doesn't have the surface array spacing bit so it's not possible to select this layout. I think it was only used in order to make it pick a tightly-packed qpitch value that doesn't include space for the mipmaps. However this won't be necessary after the next patch because it will automatically pick a packed qpitch value whenever first_level==last_level. It is better to remove this layout entirely on Gen8+ because although it can effectively be implemented with a small qpitch value when there are no mipmaps it isn't possible to support the case where there are mipmaps because in that case the layout is very different. It could be good to make a similar change for Gen8 if we also change the layouting code to pick the qpitch value in a similar way. v2: Make the commit message and comments more convincing Reviewed-by: Ben Widawsky <[email protected]> Tested-by: Ben Widawsky <[email protected]>
* i965: Issue perf_debug messages for unsynchronized maps on !LLC systems.Kenneth Graunke2015-04-171-5/+11
| | | | | | | | | | | | | | | | | We haven't implemented proper unsynchronized map support on !LLC systems (pre-SNB, Atom). MapBufferRange with GL_MAP_UNSYNCHRONIZE_BIT will actually do a synchronized map, probably killing performance. Also warn on BufferSubData, when we should be doing an unsynchronized upload, but instead have to do a synchronous map. v2: Only complain if the buffer is actually busy - we use unsynchronized maps internally for vertex upload and such, but expect those to not be busy. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Tested-by: Ben Widawsky <[email protected]>
* i965: Make shader_time store names/ids instead of referencing shaders.Kenneth Graunke2015-04-172-37/+19
| | | | | | | | | | | | | | | | | | | | | Jason noticed that shader_time was bumping the reference count on the gl_shader_program and gl_program structures, in code called during compilation. Not only were these never unreferenced, but it meant fragment shaders might be referenced twice (SIMD8 and SIMD16)...or only once. We don't actually need the programs. We just need their numeric ID and their language (GLSL/ARB/FF) or KHR_debug label. If there's a label, we have to strdup it since the underlying program could be deleted. To be fair, we're not exactly cleaning that up either, but we at least ralloc it out of the shader_time arrays, so if we ever bother cleaning those up, they'll go away properly. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Delete some unnecessary code in brw_report_shader_time().Kenneth Graunke2015-04-171-6/+1
| | | | | | | | | | | | | It is true that a gl_shader_program with ID 0 will be a fixed-function fragment program; a gl_program with ID 0 but NULL gl_shader_program means that it's a fixed-function vertex shader. But that's not terribly interesting or relevant to what we're doing. We just need to know that ID 0 means "fixed function". Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Make shader_time use 0 instead of -1 for "no meaningful ID".Kenneth Graunke2015-04-171-8/+6
| | | | | | | | | | | | 0 is not a valid GLSL shader or ARB program ID. For some reason, shader_time used -1 instead...so we had code to detect 0, then override it to -1. We can just delete that. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* adjust a couple of ifdefs to handle NetBSD correctlyTobias Nygren2015-04-171-1/+1
| | | | | Acked-by: Matt Turner <[email protected]> Signed-off-by: Tobias Nygren <[email protected]>
* i965: Render R16G16B16X16 as R16G16B16A16Anuj Phogat2015-04-171-0/+6
| | | | | | | | | | This enables using _mesa_meta_pbo_TexSubImage() to upload data to R16G16B16X16 texture. Earlier it fell back to slower paths. Jenkins run shows no piglit regressions. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Update the comment about platforms supporting blorpAnuj Phogat2015-04-171-2/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/fs: Change SEL and MOV types as needed to propagate source modifiersJason Ekstrand2015-04-171-4/+30
| | | | | | | | | | | | | | | | | | | | SEL and MOV instructions, as long as they don't have source modifiers, are just copying bits around. This commit adds support to copy propagation to switch the type of a SEL or MOV instruction as needed so that it can propagate source modifiers. This is needed because NIR generates integer SEL and MOV instructions whenver it doesn't know what else to generate. shader-db results with NIR: total FS instructions in shared programs: 4360910 -> 4360186 (-0.02%) FS instructions in affected programs: 59094 -> 58370 (-1.23%) helped: 341 HURT: 0 GAINED: 2 LOST: 0 Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Use the source type when looking for UD negations in copy propJason Ekstrand2015-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There can be problems with floats and conditional modifiers when copy-propagating a negated UD source. The problem arises when a source modifier is applied to a UD value. In this case, a 33-bit representation is internally used. If you do the following: 1: mov foo:UD 7U 2: mov bar:UD -foo:UD 3: mov out:F bar:UD the out register will have the value (float)(unt32_t)-7 which is some very large floating-point number. However, if we allow copy-propagation of the second mov, we get 1: mov foo:UD 7U 3: mov out:f -bar:UD and, since the negation is computed in 33-bits, we get a value of -7.0f which is clearly not the same. This is a similar problem if the instruction has a conditional modifier where the 33-bit value is used in the comparison and not the 32-bit version. Previously, we checked the source to be copied for the negate and then checked the source being propagated to for the type. This isn't quite what we want because we are really just looking for negated UD sources. A check later in the file ensures that both ends of the propagate have the right type so it works. However, if we relax the restriction that both ends of the propagation have the same type, it ends up causing us to bail early in cases we don't want. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Rewrite ir_tex to ir_txl with lod 0 for vertex shadersKristian Høgsberg2015-04-161-0/+9
| | | | | | | | | | | | | | | | The ir_tex opcode turns into a sample or sample_c message, which will try to compute derivatives to determine the lod. This produces garbage for non-fragment shaders where the sample coordinates don't correspond to subspans. We fix this by rewriting the opcode from ir_tex to ir_txl and setting the lod to 0. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89457 Cc: "10.5" <[email protected]> Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/skl: Add the header for constant loads outside of the generatorNeil Roberts2015-04-166-35/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 5a06ee738 added a step to the generator to set up the message header when generating the VS_OPCODE_PULL_CONSTANT_LOAD_GEN7 instruction. That pseudo opcode is implemented in terms of multiple actual opcodes, one of which writes to one of the source registers in order to set up the message header. This causes problems because the scheduler isn't aware that the source register is written to and it can end up reorganising the instructions incorrectly such that the write to the source register overwrites a needed value from a previous instruction. This problem was presenting itself as a rendering error in the weapon in Enemy Territory: Quake Wars. Since commit 588859e1 there is an additional problem that the double register allocated to include the message header would end up being split into two. This wasn't happening previously because the code to split registers was explicitly avoided for instructions that are sending from the GRF. This patch fixes both problems by splitting the code to set up the message header into a new pseudo opcode so that it will be done outside of the generator. This new opcode has the header register as a destination so the scheduler can recognise that the register is written to. This has the additional benefit that the scheduler can optimise the message header slightly better by moving the mov instructions further away from the send instructions. On Skylake it appears to fix the following three Piglit tests without causing any regressions: gs-float-array-variable-index gs-mat3x4-row-major gs-mat4x3-row-major I think we actually may need to do something similar for the fs backend and possibly for message headers from regular texture sampling but I'm not entirely sure. v2: Make sure the exec-size is retained as 8 for the mov instruction to initialise the header from g0. This was accidentally lost during a rebase on top of 07c571a39fa1. Split the patch into two so that the helper function is a separate change. Fix emitting the MOV instruction on Gen7. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89058 Reviewed-by: Ben Widawsky <[email protected]>
* i965/vec4: Add a helper function to emit VS_OPCODE_PULL_CONSTANT_LOADNeil Roberts2015-04-163-77/+75
| | | | | | | | | | | There were three places in the visitor that had a similar chunk of code to emit the VS_OPCODE_PULL_CONSTANT_LOAD opcode using a register for the offset. This patch combines the chunks into a helper function to reduce the code duplication. It will also be useful in the next patch to expand what happens on Gen9+. This shouldn't introduce any functional changes. Reviewed-by: Ben Widawsky <[email protected]>
* i965/fs: Combine tex/fb_write operations (opt)Ben Widawsky2015-04-143-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain platforms support the ability to sample from a texture, and write it out to the file RT - thus saving a costly send instructions (note that this is a potnential win if one wanted to backport to a tag that didn't have the patch from Topi which removed excess MOVs from LOAD_PAYLOAD - 97caf5fa04dbd2), v2: Modify the algorithm. Instead of iterating in reverse through blocks and insts, since the last block/inst is the only thing which can benefit. Rebased on top of Ken's patching modifying is_last_send v3: Rebased over almost 2 months, and Incorporated feedback from Matt: Some comment typo fixes and rewordings. Whitespace Move the optimization pass outside of the optimize loop v4: Some cosmetic changes requested from Ken. These changes ensured that the optimization function always returned true when an optimization occurred, and false when one did not. This behavior did not exist with the original patch. As a result, having the separate helper function which Matt did not like no longer made sense, and so now I believe everyone should be happy. Benchmark (n=20) %diff *OglBatch5 -1.4 *OglBatch7 -1.79 OglFillTexMulti 5.57 OglFillTexSingle 1.16 OglShMapPcf 0.05 OglTexFilterAniso 3.01 OglTexFilterTri 1.94 No piglit regressions: (http://otc-gfxtest-01.jf.intel.com:8080/view/dev/job/bwidawsk/112/) [*] I believe my measurements are incorrect for Batch5-7. If I add this new optimization, but never emit the new instruction I see similar results. v5: Remove declaration of combine_tex_header since v4 dropped that function (Ben) Remove check for impossible case of an empty block (Matt) Set dest earlier to avoid extra special-casing in generate_tex (Matt) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Only emit FS_OPCODE_PLACEHOLDER_HALT if there are discardsBen Widawsky2015-04-141-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based originally on a patch from Ken in May 2014 of the same title. Things changed enough that I didn't feel comfortable leaving his authorship. v2: Replace fp->UsesKill with wm_prog_data->uses_kill. Since Ken took the time to also explain the difference to me, here is his explanation for posterity: "fp->UsesKill indicates that a ARB_fragment_program shader uses the KIL instruction, or that a GLSL shader uses the "discard" insntruction (which are analogous). On Gen4-5, we sometimes have to simulate OpenGL's "Alpha Test" feature by emitting shader code that implicitly does a "discard" instruction. In the key setup, we do: /* key->alpha_test_func means simulating alpha testing via discards, * so the shader definitely kills pixels. */ prog_data.uses_kill = fp->program.UsesKill || key->alpha_test_func; Even though the shader may not technically contain a "discard", we need to act as if it does. I've also been trying to move the i965 state setup code to use brw_wm_prog_key for everything, rather than poking at core Mesa's gl_program/gl_fragment_program/gl_shader/gl_shader_program structures. --Ken" Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Create a has_side_effects for fs_instBen Widawsky2015-04-142-0/+7
| | | | | | | | | | | | | | | | | | | When an instruction has a side effect, it impacts the available options when reordering an instruction. As the EOT flag is an implied write to the render target in the FS, it can be considered a side effect. This patch shouldn't actually have any impact on the current code since the EOT flag implies that the opcode is already one with side effects, FS_OPCODE_FB_WRITE. The next patch however will introduce an optimization whereby the EOT flag can occur with an opcode SHADER_OPCODE_TEX, and as that instruction will perform the same implied write to the render target, it cannot be reordered. v2: Remove extra whitespace (Matt) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-1424-72/+72
| | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Acked-by: Matt Turner <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i915: replace __FUNCTION__ with __func__Marius Predut2015-04-1424-107/+107
| | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Acked-by: Matt Turner <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* swrast: replace __FUNCTION__ with __func__Marius Predut2015-04-142-3/+3
| | | | | | | | | | | Consistently just use C99's __func__ everywhere. The patch was verified with Microsoft Visual studio 2013 redistributable package(RTM version number: 18.0.21005.1) Next MSVC versions intends to support __func__. No functional changes. Acked-by: Matt Turner <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965/fs: Correct mistake in determining whether a MUL is negated.Matt Turner2015-04-141-1/+1
| | | | | | | | | a * b is equivalent to -a * -b, and the previous code was failing at that. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89961 Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/skl: Use an exec size of 8 to initialise the message headerNeil Roberts2015-04-142-2/+2
| | | | | | | | | | | | | | | | | | Commit e93566a15c61c33faa changed the message header code needed to make Skylake use SIMD4x2 so that it uses a register with width 4 instead of 8 as the source register in the send message. However it also changed the width for the dest in the MOV instruction which is used to initialise the header register with the values from g0. The width of the destination is used to determine the exec size in brw_set_dest so this would end up making the MOV have an exec size of 4. I think this would end up leaving the top half of the register uninitialised. The top half of the header has meaningful values so this probably isn't a good idea. This patch just casts the dest register for the MOV instruction back to a vec8 to fix it. It doesn't cause any changes to a Piglit run. Reviewed-by: Ben Widawsky <[email protected]>
* i965/fs: Always invert predicate of SEL with swapped argumentsIan Romanick2015-04-141-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Commit b616164 added an optimization of b2f generation of a comparison. It also included an extra optimization of one of the comparison values is a constant of zero. The trick was that some value was known to be zero, so that value could be used in the SEL instruction instead of potentially loading 0.0 into a register. This change switched the order of the arguments to the SEL, and, for some unknown reason, I thought that the predicate should therefore only be inverted for the == case. Clearly, it should always be inverted. Fixes piglit fs-notEqual-of-expression.shader_test and fs-equal-of-expression.shader_test. v2: Don't do the "register already has zero" optimization for the '== 0' case. In that case, the register does not have zero when we want to produce a zero result. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89722 Reviewed-by: Kenneth Graunke <[email protected]> [v1] Tested-by: Lu Hua <[email protected]>
* i965: Implement proper workaround for Gen4 GPU CONSTANT_BUFFER hangs.Kenneth Graunke2015-04-141-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | I finally managed to dig up some information on our mysterious GPU hangs. A wiki page from the Crestline validation team mentions that they found a GPU hang in "Serious Sam 2" (on Windows) with remarkably similar conditions to the ones we've seen in Google Chrome and glmark2. Apparently, if WM_STATE has "PS Use Source Depth" enabled, CC_STATE has most depth state disabled, and you issue a CONSTANT_BUFFER command and immediately draw, the depth interpolator makes a small mistake that leads to hangs. Most of the traces I looked at contained a CONSTANT_BUFFER packet immediately followed by 3DPRIMITIVE, or at least very few packets. It appears they also have "PS Use Source Depth" enabled - either at the hang, or a little before it. So I think this is our bug. The workaround is to emit a non-pipelined state packet after issuing a CONSTANT_BUFFER packet. This is really similar to the workaround I developed in commit c4fd0c9052dd391d6f2e9bb8e6da209dfc7ef35b. v2: Fix word-wrapping issues. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fix INTEL_DEBUG=shader_time for SIMD8 VS.Kenneth Graunke2015-04-141-0/+3
| | | | | | | | | In commit 4ebeb71573ad44f7657810dc5dd2c9030e3e63db, I deleted the emit_shader_time_end() call in emit_urb_writes(). But I failed to add it to run_vs(), as I intended. So no data was recorded at all. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Flush batchbuffer containing the query on glQueryCounter.Mathias Froehlich2015-04-131-0/+2
| | | | | | | | | | | | | This change fixes a regression with timer queries introduced with commit 3eb6258. There the pending batchbuffer is flushed only if glEndQuery is executed. This present change adds such a flush to glQueryCounter which also schedules a value query just like glEndQuery does. The patch fixes GPU timer queries going mad from within osgviewer. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Mathias Froehlich <[email protected]> Cc: [email protected]
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