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* i965: Complain about variable index lowering when INTEL_DEBUG=perf.Kenneth Graunke2012-09-291-2/+8
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Dump linked shaders on MESA_GLSL=dump.Kenneth Graunke2012-09-291-0/+9
| | | | | | | | | | | Often, the original shader IR isn't terribly interesting because a lot of crucial optimizations haven't been done (such as inlining built-ins). ir_to_mesa used to print this out for us, but since we don't use it, we have to do it ourselves. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel/i965: Disable SampleAlphaToOne if dual source blending enabledAnuj Phogat2012-09-291-2/+11
| | | | | | | | | | | From SandyBridge PRM, volume 2 Part 1, section 12.2.3, BLEND_STATE: DWord 1, Bit 30 (AlphaToOne Enable): "If Dual Source Blending is enabled, this bit must be disabled" Note: This is a candidate for stable branches. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: brwInitVtbl needs to know the chipset generationIan Romanick2012-09-282-0/+6
| | | | | | Fixes major regressions since de958de. Signed-off-by: Ian Romanick <[email protected]>
* i915: Don't free the intel_context structure when intelCreateContext fails.Ian Romanick2012-09-281-3/+0
| | | | | | | | | | intelDestroyContext will eventually be called, and it will clean things up. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53618
* i965: Don't free the intel_context structure when intelCreateContext fails.Ian Romanick2012-09-281-3/+2
| | | | | | | | | | | | | intelDestroyContext will eventually be called, and it will clean things up. The call to brwInitVtbl is moved earlier so that intelDestroyContext can call the device-specific destructor. This also makes the code look more like the i915 code. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54301
* intel: Don't call intelDestroyContext if there is no context to destroyIan Romanick2012-09-281-1/+3
| | | | | | | | | | | | Some error paths in the device-specific context creation functions can exit before the deintel_context structure is allocated. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53618 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54301
* dri_util: Use calloc to allocate __DRIcontextIan Romanick2012-09-281-1/+1
| | | | | | | | | | | | | | | The __DRIcontext contains some pointers, and some drivers check for them to be NULL in some failure paths. Instead of sprinkling NULL assignments across the various drivers, just zero out the whole thing. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-and-tested-by: Kenneth Graunke <[email protected]> Tested-by: Lu Hua <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53618 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54301
* intel: Fix yet-another-bug in intel_texsubimage_tiled_memcpyChad Versace2012-09-281-0/+2
| | | | | | | | | | | | | | | | | | | | The most recent commit that touched this function, commit b1d0fe022dc4826dadce014ab8fe062a82f75a16 Author: Chad Versace <[email protected]> Date: Wed Sep 26 11:05:12 2012 -0700 intel: Fix segfault in intel_texsubimage_tiled_memcpy did fix the segfault, but introduced yet another bug. From Anholt: """You need to still test format/type, because that's the incoming format (e.g. GL_RGBA/GL_FLOAT) that you're trying to memcpy.""" This patch re-introduces the checks on the incoming format and type. Note: This is a candidate for the 9.0 branch. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Don't advertise GLX_SWAP_COPY_OMLChad Versace2012-09-271-6/+6
| | | | | | | | This patch removes all gl_config's with swapMethod=GLX_SWAP_COPY_OML. When page flipping, we are unable to comply with swap-copy semantics. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Remove stale comment about rebuilding tnl_program.Eric Anholt2012-09-271-7/+0
| | | | | | It gets built in Mesa core before we're called these days. Reviewed-and-tested-by: Kenneth Graunke <[email protected]>
* i965: Add a comment explaining one of the brw_draw_upload.c loops.Eric Anholt2012-09-271-0/+4
| | | | Reviewed-and-tested-by: Kenneth Graunke <[email protected]>
* i965: Remove broken non-interleaved-to-interleaved upload code.Eric Anholt2012-09-271-50/+2
| | | | | | | | | | | This failed when all the uploads to occur were uniform-type vertex data (like glColor4f being active across a DrawArrays), because it would upload 1 element instead of 1 element per vertex. There was no citation for how this code helped any particular application, and it breaks ETQW, so just remove it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47170 NOTE: This is a candidate for the 9.0 and 8.0 branches. Reviewed-and-tested-by: Kenneth Graunke <[email protected]>
* intel: Remove dead intel_format_to_rb_datatype.Eric Anholt2012-09-272-52/+0
| | | | | | This was for some of the old spans-related code that is now gone. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Mark some file-local code as static.Eric Anholt2012-09-279-18/+9
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Mark brw_disasm.c tables as static const.Eric Anholt2012-09-271-56/+44
| | | | | | v2: Make the strings in the tables const, too. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use visibility cflags on the driver code.Eric Anholt2012-09-271-0/+1
| | | | | | | | | The only symbols that need to be public (those in intel_screen.c that the loader looks for) are already marked public. Saves 100k of compiled driver size. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vp: Remove support for non-ARB_vp, non-NV_vp opcodes.Eric Anholt2012-09-271-86/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vp: Remove support for relative addressing of destination registers.Eric Anholt2012-09-271-83/+7
| | | | | | | This was added for GLSL support back in the day. It's prohibited by both ARB_vp and NV_vp. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vp: Remove support for reading destination registers.Eric Anholt2012-09-272-64/+4
| | | | | | It's prohibited by ARB_vp and NV_vp, and not used by fixed function t&l. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vp: Remove support for GLSL flow control from the old VS backend.Eric Anholt2012-09-271-83/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Fix segfault in intel_texsubimage_tiled_memcpyChad Versace2012-09-271-2/+1
| | | | | | | | | | | | | | | The function segfaulted when a game called glTexSubImage2D on a texture with internalformat/format/type = GL_SLUMINANCE8/GL_BGRA/GL_UNSIGNED_BYTE. The function only supports MESA_FORMAT_ARGB8888 and returns early if it detects an unsupported format. Clearly, its detection condition was insufficient. This patch fixes it to explicity check for MESA_FORMAT_ARGB8888. Note: This is a candidate for the 9.0 branch (fixes 413c491). Reviewed-and-tested-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Do texture swizzling in hardware on Haswell.Kenneth Graunke2012-09-262-5/+52
| | | | | | | | | | | | | | | | | | | Haswell supports EXT_texture_swizzle and legacy DEPTH_TEXTURE_MODE swizzling by setting SURFACE_STATE entries. This means we don't have to bake the swizzle settings into the shader code by emitting MOV instructions, and thus don't have to recompile shaders whenever the swizzles change. Unfortunately, we can't handle GL_ALPHA this way: unlike all the others, which store the comparison result in the .r channel (and possibly others as well), GL_ALPHA puts it in the .a channel. The GLSL 1.30+ style functions which return a float always simply return the .r channel, which would be zero if we handled this as a surface override. In this case, fall back to doing it the old way. DEPTH_TEXTURE_MODE = GL_ALPHA isn't an interesting performance path anyway. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Refactor texture swizzle generation into a helper.Kenneth Graunke2012-09-263-49/+60
| | | | | | | It's going to be reused in a second place soon. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* intel: Fix size of temporary etc1 bufferChad Versace2012-09-261-3/+4
| | | | | | | | | | | | | | | | Fixes valgrind errors in piglit test oes_compressed_etc1_rgb8_texture-miptree: an invalid write in _mesa_store_compressed_store_texsubimage() at line 4406 and invalid reads in texcompress_etc_tmp.h:etc1_parse_block(). The calculation of the size of the temporary etc1 buffer allocated by intel_miptree_map_etc1() was incorrect. Sometimes the allocated buffer was too small, sometimes too large. This patch corrects the size to that expected by _mesa_store_compressed_store_texsubimage(). Note: This is candidate for the 9.0 branch. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Improve teximage perf for Google Chrome paint rects (v3)Chad Versace2012-09-253-0/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reduces the time spent in glTexImage and glTexSubImage by over 5x on Sandybridge for the workload described below. It adds a new fast path for glTexImage2D and glTexSubImage2D, intel_texsubimage_tiled_memcpy, which is optimized for Google Chrome's paint rectangles. The fast path is implemented only for 2D GL_BGRA textures for chipsets with a LLC. === Performance Analysis === Workload description: Personalize your google.com page with a wallpaper. Start chromium with flags "--ignore-gpu-blacklist --enable-accelerated-painting --force-compositing-mode". Start recording with chrome://tracing. Visit google.com and wait for page to finish rendering. Measure the time spent by process CrGpuMain in GLES2DecoderImpl::HandleTexImage2D and HandleTexSubImage2D. System config: cpu: Sandybridge Mobile GT2+ (0x0126) kernel 3.4.9 x86_64 chromium 21.0.1180.89 (154005) Statistics: | N Median Avg Stddev --------------|------------------------- before (msec) | 8 472.5 463.75 72.6 after (msec) | 8 78.0 79.6 5.7 Arithmetic difference at 95.0% confidence: -384.1 +/- 55.2 msec -82.8% +/- 11.9% Ratio at 95.0% confidence: 5.81 +/- 0.119 v2: - Replace check for `intel->gen >= 6` with `intel->has_llc`, per danvet. - Fix typo in comment, s/throuh/through/. - Swap 'before' and 'after' rows in stat table. v3: - If the current batch references the bo, then flush batch before mapping the bo. Found by Chris. - Restrict supported texture images to level 0 of target GL_TEXTURE_2D. This avoids an arithmetic bug in calculating image offsets within the miptree, found by Paul. This restriction does not diminish this patch's benefit to Chrome OS performance. - Use less instructions for bit6 swizzling, suggested by Paul. - Remove erroneous comment about Y-tiling, for Paul. - Print perf_debug messages when flushing and stalling. - Update stats in commit message; run workload under a release build rather than a debug build. Note: This is a candidate for the 9.0 branch. Acked-by: Eric Anholt <[email protected]> CC: Stéphane Marchesin <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Allow fast depth clears if scissoring doesn't do anything.Kenneth Graunke2012-09-251-1/+13
| | | | | | | | | | | | | | | | A game we're working with leaves scissoring enabled, but frequently sets the scissor rectangle to the size of the whole screen. In that case, scissoring has no effect, so it's safe to go ahead with a fast clear. Chad believe this should help with Oliver McFadden's "Dante" as well. v2/Chad: Use the drawbuffer dimensions rather than the miptree slice dimensions. The miptree slice may be slightly larger due to alignment restrictions. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]> Reviewed-and-tested-by: Oliver McFadden <[email protected]>
* i965: Don't spill "smeared" registers.Paul Berry2012-09-251-0/+15
| | | | | | | | | | | | Fixes an assertion failure when compiling certain shaders that need both pull constants and register spilling: brw_eu_emit.c:204: validate_reg: Assertion `execsize >= width' failed. NOTE: This is a candidate for release branches. Signed-off-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Fix sRGB MSAA resolves.Paul Berry2012-09-242-8/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e2249e8c4d06a85d6389ba1689e15d7e29aa4dff (i965/blorp: Add support for blits between SRGB and linear formats) changed blorp to always configure surface states for in linear format (even if the underlying surface is sRGB). This allowed sRGB-to-linear and linear-to-sRGB blits to occur without causing the image to be inappropriately brightened or darkened. However, it broke sRGB MSAA resolves, since they rely on the destination buffer format being sRGB in order to ensure that samples are averaged together in sRGB-correct fashion. This patch fixes the problem by instead configuring the source buffer to use the *same* format as the destination buffer. This ensures that the image won't be brightened or darkened, but preserves proper sRGB averaging. Fixes piglit tests "EXT_framebuffer_multisample/accuracy srgb". Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55265 NOTE: This is a candidate for stable release branches. Reviewed-by: Eric Anholt <[email protected]> Reviewed-and-tested-by: Kenneth Graunke <[email protected]>
* i965/blorp: Increase Y alignment for multisampled stencil blits.Paul Berry2012-09-241-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is a band-aid fix for a bug in commit 5fd67fa (i965/blorp: Reduce alignment restrictions for stencil blits), which causes multisampled stencil blits to work incorrectly on Sandy Bridge. When blitting to or from a normal stencil buffer, we have to use a coordinate transformation that swizzles coordinates to account for the fact that stencil buffers use W tiling, but the most similar tiling format available for textures and render targets is Y tiling. The differences between W and Y tiling cause pixels to be scrambled within a block of size 8x4 (width x height) as measured relative to a W tile, or 16x2 as measured relative to a Y tile. So in order to make sure that pixels at the edges of the blit aren't lost, we need to align the rendering rectangle (and the buffer sizes) to multiples of the 8x4 block size. This alignment happens in the brw_blorp_blit_params constructor, whereas the determination of how to swizzle the coordinates happens during code generation, in the brw_blorp_blit_program class. When blitting to or from a multisampled stencil buffer, the coordinate swizzling is more complex, because it has to account for the interleaving pattern of samples, which uses 4x4 blocks for 4x MSAA and 8x4 blocks for 8x MSAA. The end result is that if multisampling is in use, the 16x2 block size (relative so a Y tile) needs to be expanded to 16x4, and the corresponding size relative to a W tile expands to 8x8. The problem doesn't affect Ivy Bridge severely enough to crop up in Piglit tests because on Ivy Bridge we have to disable multisampling when blitting *to* a multisampled stencil buffer (the blorp compiler generates code to compensate for the fact that multisampling is disabled). However I suspect a bug is still present because we don't disable multisampling when blitting *from* a multisampled stencil buffer. This patch fixes the problem by doubling the vertical alignment requirement when blitting to or from a multisampled stencil buffer, and multisampling has not been disabled. In the long run I would like to rework the brw_blorp_blit_params constructor--it's difficult to follow and has had several subtle bugs like this one. However this band-aid fix should be suitable for cherry-picking to release branches. Fixes Piglit tests "unaligned-blit {2,4} stencil {msaa,upsample}" on Sandy Bridge. NOTE: This is a candidate for stable release branches. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Fix narrowing warnings.Paul Berry2012-09-211-3/+3
| | | | | | | | | | | Blorp has to convert rectangle coordinates from integers to floats in order to send them down the GPU pipeline. Recent versions of GCC issue a warning for this, since a float is not capable of precisely representing all possible 32-bit integer values. Suppress the warning with an explicit type cast in the case of blorp, since rectangle coordinates will never be large enough to cause a loss of precision. Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove brw_set_predicate_inverse(p, true) from scratch offset codeKenneth Graunke2012-09-211-1/+0
| | | | | | | | | | | | | | Given that it exists between a push/pop of instruction state, this call can only affect the MOV or ADD instruction generated just below it. Neither of those instructions are predicated, so it makes no sense to ask for the inverse predicate. This fixes grumblings from the simulator debugger, which was complaining about an invalid predicate. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/blorp: Add support for blits between SRGB and linear formats.Kenneth Graunke2012-09-202-4/+8
| | | | | | | | | | | | Fixes colorspace issues in L4D2 when multisampling is enabled (the scene was far too dark, but the flashlight area was way too bright). The nVidia and AMD binary drivers both allow this kind of blit. NOTE: This is a candidate for the 9.0 branch. Reviewed-by: Paul Berry <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* ra: Add q_values parameter to ra_set_finalize()Tom Stellard2012-09-192-2/+2
| | | | | | This allows the user to pass precomputed q values to the allocator. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Stop putting 8 NOPs after each prorgam.Eric Anholt2012-09-171-8/+0
| | | | | | | | | | | | | As far as I can see, the intention of the requirement that we do so is to prevent instruction prefetch from wandering out into either unmapped memory or memory with a different caching type, and hanging the chip. The kernel makes sure that the page after your BO has a valid page of the same caching type, which meets this requirement, so there's no need to waste space between our programs (and in instruction cache) on this. Saves another 9kb instructions in l4d2 shaders. Acked-by: Kenneth Graunke <[email protected]>
* i965: Test instruction compaction on gen7Eric Anholt2012-09-172-10/+23
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* i965: Add support for instruction compaction on Gen7.Kenneth Graunke2012-09-173-33/+220
| | | | | | | | | | Reduces l4d2 program size from 1195kb to 919kb. Improves performance by 0.22% +/- 0.11% (n=70). v2: Rebase on compaction v2, fix up flag reg handling (by anholt). v3: Fix uncompaction of the flag register number. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Support instruction compaction between control flow.Eric Anholt2012-09-171-28/+92
| | | | Reviewed-by: Paul Berry <[email protected]>
* i965: Add support for instruction compaction.Eric Anholt2012-09-1710-8/+946
| | | | | | | | | | | | | | | This reduces program size by using some smaller encodings for common bit patterns in the Gen ISA, with the hope of making programs fit in the instruction cache better. v2: Use larger bitshifts for the uncompressed field setups, in line with the way it's described in the spec. Consistently name a brw_compile "p" like all other code. Add a couple more tests. Consistently call things "compacted" not "compressed" (which is a different feature). Drop the explicit check for not compacting SENDs, which is unjustified and already implied by our lack of support for immediate values. Reviewed-by: Paul Berry <[email protected]>
* i965: Prepare the break/cont uip/jip setting for compacted instructions.Eric Anholt2012-09-171-14/+43
| | | | | | | | | The first cut at instruction compaction won't compact things that would change control flow jump distances, but we do need to still be able to walk the instruction stream, which involves jumping by 8 or 16 bytes between instructions. Reviewed-by: Paul Berry <[email protected]>
* i965: Move program dump to a helper function in brw_eu.c.Eric Anholt2012-09-177-55/+40
| | | | | | | | | It's going to get more complicated when we do instruction compaction. This also introduces putting the program offset in the output. v2: Use next_insn_offset in brw_get_program(), too. Reviewed-by: Paul Berry <[email protected]>
* i965: Make a linkable library for the contents of i965_dri.so.Eric Anholt2012-09-172-5/+13
| | | | | | | | To do unit testing of i965, we want to be able to link against the driver's symbols and prod them. If we don't have a separate lib from our loadable module, libtool gets super whiny. Acked-by: Paul Berry <[email protected]>
* dri: Reuse dri_test.c for stub glapi symbols for unit testing.Eric Anholt2012-09-172-1/+9
| | | | | | | | This file is used to provide stubs for the link test in gallium dri drivers. But the same stubs without the main can be used for making unit tests for code in a dri driver. Acked-by: Paul Berry <[email protected]>
* i965: Clear brw_compile on setup.Eric Anholt2012-09-171-0/+2
| | | | | | | | I noticed in valgrind that p->single_program_flow was used while uninitialized. Everything else zeroed out brw_compile, but this is better API. Reviewed-by: Paul Berry <[email protected]>
* mesa: remove FEATURE_APPLE_object_purgeable define.Oliver McFadden2012-09-151-4/+0
| | | | | Signed-off-by: Oliver McFadden <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: remove FEATURE_EXT_framebuffer_blit define.Oliver McFadden2012-09-152-4/+0
| | | | | Signed-off-by: Oliver McFadden <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: remove FEATURE_OES_EGL_image define.Oliver McFadden2012-09-158-29/+0
| | | | | Signed-off-by: Oliver McFadden <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: remove FEATURE_EXT_framebuffer_object define.Oliver McFadden2012-09-152-4/+0
| | | | | Signed-off-by: Oliver McFadden <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* vbo: add a prefix to count_tessellated_primitivesDave Airlie2012-09-151-1/+1
| | | | | | | | | Just to make it consistent with the rest of vbo, since it would be an exported symbol anyways. Reviewed-by: Matt Turner <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Fix out-of-order sampler unit usage in ARB fragment programs.Kenneth Graunke2012-09-122-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | ARB fragment programs use texture unit numbers directly, unlike GLSL which has an extra indirection. If a fragment program only uses one texture assigned to GL_TEXTURE1, SamplersUsed will only contain a single bit, which would make us only upload a single surface/sampler state entry. However, it needs to be the second entry. Using _mesa_fls() instead of _mesa_bitcount() solves this. For ARB programs, this makes num_samplers the ID of the highest texture unit used. Since GLSL uses consecutive integers assigned by the linker, _mesa_fls() should give the same result as _mesa_bitcount().. Fixes a regression since 85e8e9e000732908b259a7e2cbc1724a1be2d447, which caused GPU hangs in ETQW (and probably others), as well as breaking piglit test fp-fragment-position. v2: Add a comment, as suggested by Matt. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54098 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54179 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Tested-by: meng <[email protected]>
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