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* i965: Fix brw_link_shader to return false rather than NULL.Kenneth Graunke2012-08-251-1/+1
| | | | | | | | | | Fixes brw_shader.cpp:101:9: warning: converting to non-pointer type 'GLboolean {aka unsigned char}' from NULL [-Wconversion-null] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-with-great-enthusiasm-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by Eric Anholt <[email protected]>
* mesa: add texture target field to ChooseTextureFormat() driver hookBrian Paul2012-08-245-3/+8
| | | | | | | | | This will let us choose the actual hardware format depending on the type of texture. v2: fixup radeon, nouveau, intel and swrast drivers too Reviewed-by: Eric Anholt <[email protected]>
* i965: don't clear resolve map when doing fast depth clears.Paul Berry2012-08-241-4/+2
| | | | | | | | | | | | | | | | | | Previously, when performing a fast depth clear, we would also clear the miptree's resolve map. This destroyed important information, since the resolve map contains information about needed resolves for all levels and layers of the miptree, whereas a depth clear only applies to a single level/layer combination at a time. As a result, resolves would sometimes fail to occur, leading to incorrect rendering. Fixes rendering artifacts with shadow maps in Unigine Heaven and Unigine Sanctuary. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50270 Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/HiZ: remove assertion from intel_resolve_map_set().Paul Berry2012-08-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | There are three possible resolve map states for each (level, layer) of a depth miptree: "needs HiZ resolve", "needs depth resolve", and "needs neither". When HiZ was first implemented on i965, any attempt to directly transition between "needs HiZ resolve" and "needs depth resolve" without passing through the "needs neither" state would have been a bug indicating that a necessary resolve hadn't been performed. Accordingly, intel_resolve_map_set() contained an assertion to verify that no such direct transition happened. However, now that we support fast depth clears, there is a valid transition from the "needs HiZ resolve" to the "needs depth resolve" state. When doing a fast depth clear, the old state of the buffer is irrelevant, since we are completely replacing it with the clear value, so it is not necessary to do any resolves before clearing--we can transition, if necessary, directly from the "needs HiZ resolve" state to the "needs depth resolve" state. To avoid spurious assertions in this valid case, this patch just removes the assertion. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* mesa: new _mesa_num_tex_faces() helperBrian Paul2012-08-244-8/+9
| | | | | Not a real big help now, but will be useful for the GL_ARB_texture_cube_map_array extension in the future.
* i965/msaa: Add sample-alpha-to-coverage support for multiple render targetsAnuj Phogat2012-08-234-2/+43
| | | | | | | | | | | | | | | | | | | | | | Render Target Write message should include source zero alpha value when sample-alpha-to-coverage is enabled for an FBO with multiple render targets. Source zero alpha value is used as fragment coverage for all the render targets. This patch makes piglit tests draw-buffers-alpha-to-coverage and alpha-to-coverage-no-draw-buffer-zero to pass on Sandybridge. No regressions are observed with piglit all.tests. V2: Revert all the changes made in emit_color_write() function to include src0 alpha for targets > 0. Now handling this case in a if block. V3: Correctly calculate the instruction length for buffer zero. Properly handle the case of dual_src_blend when alpha-to-coverage is enabled. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Fix bug in the old FS backend's projtex() calculation.Eric Anholt2012-08-171-3/+1
| | | | | | | | | | | | In the old backend, we looked at any FS attribute's proj_attrib_mask bits, not just texcoords. Now that we have _mesa_vert_result_to_frag_attrib(), we can fill in the other FS inputs with correct proj_attrib_mask info. NOTE: This is a candidate for stable branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46644 Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add ARB_texture_rgb10_a2ui supportJordan Justen2012-08-142-0/+2
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* intel: Fix rendering to a multisample front bufferChad Versace2012-08-141-0/+10
| | | | | | | | We need to downsample before flushing BUFFER_FAKE_FRONT_LEFT to BUFFER_FRONT_LEFT in intel_flush_front. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Clean up intel_flush_frontChad Versace2012-08-141-4/+5
| | | | | | | | Stop repeating ourselves. Replace the 4 instances of `driContext->driDrawablePriv` with `driDrawable`. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Refactor intel_downsample_for_dri2_flushChad Versace2012-08-143-30/+34
| | | | | | | | Move it from intel_screen.c to intel_context.c. Redeclare as non-static. A future commit will use it in multiple files. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* dri_util: Compare against the correct API enumsIan Romanick2012-08-141-2/+2
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Implement ARB_texture_storageIan Romanick2012-08-142-0/+27
| | | | | | | | This is basically cut-and-paste from the swrast implementation, and it could probably be (slightly) more optimal. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix the scaling of seconds to ms in perf debug.Eric Anholt2012-08-132-2/+2
| | | | *headdesk*
* i965: Validate API and version in brwCreateContextIan Romanick2012-08-133-5/+46
| | | | | | | v2: Use base-10 for versions like gl_context::Version. Suggested by Ken. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i915: Validate API and version in i915CreateContextIan Romanick2012-08-133-1/+40
| | | | | | | v2: Use base-10 for versions like gl_context::Version. Suggested by Ken. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i830: Validate API and version before calling i830CreateContextIan Romanick2012-08-131-0/+18
| | | | Signed-off-by: Ian Romanick <[email protected]>
* intel: In the i915 driver, the chipset cannot be i965Ian Romanick2012-08-131-8/+5
| | | | | | | | In the i965 dirver, the chipset must be i965. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* dri: Pass API_OPENGL_CORE through to the driversIan Romanick2012-08-136-20/+100
| | | | | | | | | | | This forces the drivers to do at least some validation of context API and version before creating the context. In r100 and r200 drivers, this means that they don't do any post-hoc validation. v2: Actually reject compatibility profile 3.2+ contexts. Thanks Ken. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Reserve enough space to finish occlusion queries on Gen6.Kenneth Graunke2012-08-122-1/+15
| | | | | | | | | | | | | | | | | | | After realizing that brw_finish_batch emitted some final PIPE_CONTROLs to record occlusion queries, Chris noted that we probably hadn't reserved enough space to actually emit them. Reserving a full 60 bytes seems a bit harsh, since we only need that much if occlusion queries are actually active. Plus, 28 bytes would be sufficient for Gen7, and 24 for Gen4-5. We could optimize this in the future, but it doesn't seem too critical. NOTE: This is a candidate for stable release branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53311 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Move finish_batch() call before MI_BATCH_BUFFER_END and padding.Kenneth Graunke2012-08-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | On Gen4+, brw_finish_batch() calls brw_emit_query_end(), which emits some extra PIPE_CONTROLs to capture the current occlusion query data. Unfortunately, it was being called *after* _intel_batchbuffer_flush added the MI_BATCH_BUFFER_END, meaning those PIPE_CONTROLs didn't get inside the batch. Not only does this likely cause bogus occlusion query values, it can also cause crashes: with the recent change to use 64-bit depth count writes on Gen6+, we started emitting an odd-length PIPE_CONTROL, which happened after the MI_NOOP padding. This resulted in an odd-length batch buffer, which resulted in execbuf2 returning -EINVAL and the application dying with an intel_do_flush_locked failure. On older generations, finish_batch() doesn't emit any state, so this change shouldn't have any effect. Huge thanks to Chris Wilson for helping me figure this out. NOTE: This is a candidate for stable release branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=53311 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add perf debug for stalls during shader compiles.Eric Anholt2012-08-124-2/+45
| | | | | | | v2: fix bad comment from before I gave up and decided to just use doubles. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add performance debug for when the state cache gets nuked.Eric Anholt2012-08-121-1/+4
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add performance debug for shader recompiles.Eric Anholt2012-08-126-0/+103
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add performance debug for fast clear fallbacks.Eric Anholt2012-08-121-1/+9
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Add performance debug for some common GPU stalls.Eric Anholt2012-08-123-1/+19
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add performance debug for register spilling.Eric Anholt2012-08-122-0/+8
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add INTEL_DEBUG=perf for failure to compile 16-wide shaders.Eric Anholt2012-08-123-2/+11
| | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Rename INTEL_DEBUG=fall to INTEL_DEBUG=perf.Eric Anholt2012-08-127-10/+11
| | | | | | | | | I want to introduce some more debug output for performance surprises that includes fallbacks, but aren't necessarily software rasterization. Leave INTEL_DEBUG=fall in place for those that have used that flag before. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Remove unnecessary parameters CompressedTexImagePauli Nieminen2012-08-121-2/+0
| | | | | | | | | In tune with previous patches. Again there is duplication of information in function parameters that is good to remove. Signed-off-by: Pauli Nieminen <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Remove unnecessary parameters from AllocTextureImageBufferPauli Nieminen2012-08-123-11/+6
| | | | | | | | | | Size and format information is always stored in gl_texture_image structure. That makes it preferable to remove duplicate information from parameters to make interface easier to understand. Signed-off-by: Pauli Nieminen <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Remove unnecessary parameters from TexImagePauli Nieminen2012-08-123-60/+17
| | | | | | | | | | | gl_texture_image structure always holds size and internal format before TexImage driver hook is called. Those passing same information in function parameters only duplicates information making the interface harder to understand. Signed-off-by: Pauli Nieminen <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Always downsample in intel_miptree_map_multisampleChad Versace2012-08-091-3/+0
| | | | | | | | | | | | | Always downsample before mapping, even if the map mode contains GL_MAP_INVALIDATE_RANGE_BIT. If we neglect to downsample when only a subrect is mapped then the upsample in intel_miptree_unmap_multisample may write garbage to the region outside the subrect. (Eric gave my patch e88cfbb a conditional reviewed-by with the condition that it always downsample before mapping. I forgot to make that change before pushing the patch.) Signed-off-by: Chad Versace <[email protected]>
* i965/gen6+: Add support for edge flags.Eric Anholt2012-08-093-6/+51
| | | | | | | Fixes the 3 new piglit edgeflag tests. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40707 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Convert EdgeFlagPointer values appropriately for the VS on gen4.Eric Anholt2012-08-091-0/+10
| | | | | | | Fixes piglit gl-2.0/edgeflag. NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Add comment noting copy_edgeflag state dependency.Eric Anholt2012-08-091-0/+2
| | | | | | It's already in the state struct. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Add support for copying user edge flags.Eric Anholt2012-08-091-2/+11
| | | | | | | | | Fixes the glsl skinning demo regression since changing to the new GLSL compiler, and is part of fixing piglit gl-2.0-edgeflag. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50079 NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix the FS inputs setup when some SF outputs aren't used in the FS.Olivier Galibert2012-08-092-2/+25
| | | | | | | | | | | | | If there was an edge flag or a two-side-color pair present, we'd end up mismatched and read values from earlier in the VUE for later FS inputs. v2: Fix regression in gles2conform shaders generating point size. (change by anholt) Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> NOTE: This is a candidate for the 8.0 branch.
* intel: use _mesa_meta_Clear with OpenGL ES 1.1 v2Tapani Pälli2012-08-082-4/+9
| | | | | | | | | | | | | | | Patch changes i915 and i965 drivers to use fixed function version of meta clear when running on ES 1.1. This fixes rendering errors seen with Google Maps, Angry Birds and Gallery3D on Android platform. Change 88128516d43be5d25288ff5b64db63cda83c04b3 exposes all extensions internally to be available independent of GL flavour, therefore check against ARB_fragment_shader does not work. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50333 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rework the extra flushes surrounding occlusion queries.Kenneth Graunke2012-08-081-7/+4
| | | | | | | | | | | | This removes the CS stall on Ivybridge. On Sandybridge, the depth stall needs to be preceded by a non-zero post-sync op, which requires a CS stall, which needs a stall at scoreboard. Emit the full workaround. Reviewed-by: Daniel Vetter <[email protected]> Cc: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965/vs: Protect pow(x,y) MOV of y on gen4 from other instruction flags.Eric Anholt2012-08-081-0/+4
| | | | | | | | | I don't know if it was possible to trigger this bug -- we don't merge saturates into the math instruction because we're bad at coalescing currently, and there's nothing generating these with predicates. Still, let's avoid future bugs when we do smarter codegen. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Drop the confusing saturate argument to math instruction setup.Eric Anholt2012-08-088-44/+6
| | | | | | | | | | | | | | | | | | | This was ridiculous. We were ignoring the inst->header.saturate flag in the case of math and only math. On gen4, we would leave inst->header.saturate in place if it happened to be set, which would end up being applied to the implicit mov and thus trash the first argument. On gen6, we would overwrite inst->header.saturate with the saturate flag from the argument, which was not set appropriately in brw_vec4_emit.cpp, and was only not a bug due to our incompetence at coalescing saturate moves. By ripping the argument out and making saturate work just like all the other brw_eu_emit.c code generation, we can avoid both these classes of bugs. Fixes piglit fog-modes, and the new specific fs-saturate-exp2 case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48628 NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make brw_set_saturate() use stdbool.Eric Anholt2012-08-082-3/+3
| | | | | | There was a chance for brw_wm_emit.c to screw up and pass (1 << 4) instead of 1, which would get converted to 0 when stored. Instead, use stdbool which converts nonzero to true/1 like we want.
* i965: Use 64-bit writes for occlusion queries.Kenneth Graunke2012-08-081-2/+3
| | | | | | | | | | | | | | | The hardware seems to use the length of the PIPE_CONTROL command to indicate whether the write is 64-bits or 32-bits. Which makes sense for immediate writes. Daniel discovered this by writing a pattern into the query object bo and noticing that the high 32-bits were left intact, even on those pipe control writes that seemingly worked. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Refactor depth count write PIPE_CONTROLs into a helper function.Kenneth Graunke2012-08-081-68/+43
| | | | | | | | | | This consolidates the complexity in one place, which is important because it's about to get even more complicated. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Emit a CS stall before timestamp writes.Kenneth Graunke2012-08-081-0/+14
| | | | | | | | | | This implements one of the Sandybridge PIPE_CONTROL workarounds. It doesn't appear to be required for Ivybridge. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use 64-bit writes for timestamp queries.Kenneth Graunke2012-08-081-2/+3
| | | | | | | | | | | | | | | The hardware seems to use the length of the PIPE_CONTROL command to indicate whether the write is 64-bits or 32-bits. Which makes sense for immediate writes. Daniel discovered this by writing a pattern into the query object bo and noticing that the high 32-bits were left intact, even on those pipe control writes that seemingly worked. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Refactor timestamp write PIPE_CONTROLs into a helper function.Kenneth Graunke2012-08-081-50/+30
| | | | | | | | | This consolidates the complexity in one place, which is important because it's about to get even more complicated. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Make the length for PIPE_CONTROL explicit.Kenneth Graunke2012-08-084-20/+20
| | | | | | | | | | | | | | | | PIPE_CONTROL has variable length, depending upon generation and whether we want to do 32-bit or 64-bit data writes. Make it explicit, rather than hiding a length of 4 in the #define for _3DSTATE_PIPE_CONTROL. Generated by s/3DSTATE_PIPE_CONTROL/3DSTATE_PIPE_CONTROL | (4 - 2)/g. This is equivalent since the #define used to have | 2 in it. A grep through the sources shows that all instances have been converted, so it's safe to remove the | 2 from the #define. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* swrast: add missing switch case for API_OPENGL_COREBrian Paul2012-08-081-0/+2
| | | | | | To silence compiler warning. Reviewed-by: José Fonseca <[email protected]>
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