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* i965: replace brw_tess_{eval,ctrl}_program with brw_programTimothy Arceri2016-10-268-74/+18
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: replace brw_geomerty_program with brw_programTimothy Arceri2016-10-267-37/+10
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: replace brw_vertex_program with new generic brw_programTimothy Arceri2016-10-266-23/+20
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* st/mesa/r200/i915/i965: eliminate gl_fragment_programTimothy Arceri2016-10-2619-68/+66
| | | | | | | | | | Here we move OriginUpperLeft and PixelCenterInteger into gl_program all other fields have been replace by shader_info. V2: Don't use anonymous union/structs to hold vertex/fragment fields suggested by Ian. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/mesa/st/swrast: set fs shader_info directly and switch to using itTimothy Arceri2016-10-268-26/+19
| | | | | | | Note we access shader_info from the program struct rather than the nir_shader pointer because shader cache won't create a nir_shader. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: remove unused debug paramTimothy Arceri2016-10-262-17/+17
| | | | | | | | | This was accidently disabled in 832bcc3613 not long after it was added. Since it's only for gen5 and lower we might as well just remove it rather than fixing it. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: remove unused BRW_STATE_INTERPOLATION_MAP flagTimothy Arceri2016-10-262-3/+0
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965: rewrite brw_setup_vue_interpolation()Timothy Arceri2016-10-2620-125/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Here brw_setup_vue_interpolation() is rewritten not to use the InterpQualifier array in gl_fragment_program which will allow us to remove it. This change also makes the code which is only used by gen4/5 more self contained as it now has its own gen5_fragment_program struct rather than storing the map in brw_context. This means the interpolation map will only get processed once and will get stored in the in memory cache rather than being processed everytime the fs changes. Also by calling this from the fs compile code rather than from the upload code and using the interpolation assigned there we can get rid of the BRW_NEW_INTERPOLATION_MAP flag. It might not seem ideal to add a gen5_fragment_program struct however by the end of this series we will have gotten rid of all the brw_{shader_stage}_program structs and replaced them with a generic brw_program struct so there will only be two program structs which is better than what we have now. V2: Don't remove BRW_NEW_INTERPOLATION_MAP from dirty_bit_map until the following patch to fix build error. V3 - Suggestions by Jason: - name struct gen4_fragment_program rather than gen5_fragment_program - don't use enum with memset() - create interp mode set helper and simplify logic to call it - add assert when calling function to show prog will never be NULL for gen4/5 i.e. no Vulkan Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/mesa/st: eliminate gl_compute_programTimothy Arceri2016-10-264-18/+16
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* mesa/i965/i915/r200: eliminate gl_vertex_programTimothy Arceri2016-10-2612-82/+79
| | | | | | | Here we move the only field in gl_vertex_program to the ARB program fields in gl_program. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: switch vs over to shared shader_infoTimothy Arceri2016-10-262-4/+3
| | | | | | | Note we access shader_info from the program struct rather than the nir_shader pointer because shader cache won't create a nir_shader. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/mesa/st: eliminate gl_geometry_programTimothy Arceri2016-10-266-19/+16
| | | | | | We now get all the gs metadata from shader_info. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: switch gs over to shared shader_infoTimothy Arceri2016-10-261-1/+1
| | | | | | | Note we access shader_info from the program struct rather than the nir_shader pointer because shader cache won't create a nir_shader. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/mesa/st: eliminate gl_tess_eval_programTimothy Arceri2016-10-267-25/+24
| | | | | | We now get all the tes metadata from shader_info. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: switch tes over to shared shader_infoTimothy Arceri2016-10-262-8/+8
| | | | | | | Note we access shader_info from the program struct rather than the nir_shader pointer because shader cache won't create a nir_shader. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/mesa/st: eliminate gl_tess_ctrl_programTimothy Arceri2016-10-267-16/+15
| | | | | | We now get all the tcs metadata from shader_info. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: switch tcs over to shared shader_infoTimothy Arceri2016-10-262-22/+17
| | | | | | | Note we access shader_info from the program struct rather than the nir_shader pointer because shader cache won't create a nir_shader. Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: add temporary copy_shader_info() functionTimothy Arceri2016-10-261-4/+4
| | | | | | | | | | | | | This function is added here to ease refactoring towards using the new shared shader_info. Once refactoring is complete and values are set directly it will be removed. We call it from _mesa_copy_linked_program_data() rather than glsl_to_nir() so that the values will be set for all drivers. In order to do this some calls need to be moved around so that we make sure to call do_set_program_inouts() before _mesa_copy_linked_program_data() Reviewed-by: Jason Ekstrand <[email protected]>
* nir/i965/anv/radv/gallium: make shader info a pointerTimothy Arceri2016-10-2632-174/+182
| | | | | | | | | | When restoring something from shader cache we won't have and don't want to create a nir_shader this change detaches the two. There are other advantages such as being able to reuse the shader info populated by GLSL IR. Reviewed-by: Jason Ekstrand <[email protected]>
* nir: move nir_shader_info to a common compiler headerTimothy Arceri2016-10-261-1/+1
| | | | | | | This will allow use to stop copying values between structs and will also simplify handling handling these values in the shader cache. Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: modify _mesa_copy_linked_program_data() to take gl_linked_shaderTimothy Arceri2016-10-261-3/+4
| | | | | | | | | | This allows us to do some small tidy ups, but will also allow us to call a new function that copies values to a shared shader info from here. In order to make this change this function now requires _mesa_reference_program() to have previously been called. Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: add missing formats to driGLFormatToImageFormatTapani Pälli2016-10-251-0/+2
| | | | | | | | | | | Fixes following dEQP tests: dEQP-EGL.functional.image.api.create_image_gles2_tex2d_luminance dEQP-EGL.functional.image.api.create_image_gles2_tex2d_luminance_alpha Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98328
* i965: Drop nir_inputs from fs_visitor.Kenneth Graunke2016-10-241-1/+0
| | | | | | | | It's unused. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Don't use nir_assign_var_locations for VS/TES/GS outputs.Kenneth Graunke2016-10-245-62/+12
| | | | | | | | | | | Fixes spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-dvec3. v2: Remove nir_outputs field from fs_visitor (caught by Tim and Iago). Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Make split_virtual_grfs() call compact_virtual_grfs().Kenneth Graunke2016-10-241-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Post-splitting, VGRFs have a maximum size (MAX_VGRF_SIZE). This is required by the register allocator, as we have to create classes for each size of VGRF. We can (and do) allocate virtual registers larger than MAX_VGRF_SIZE, but we must ensure that they are splittable. split_virtual_grfs() asserts that the post-splitting register size is in range. Unfortunately, these trip for completely dead registers which are too large - we only set split points for live registers. So dead ones are never split, and if they happened to be too large, they'd trip asserts. To fix this, call compact_virtual_grfs() to eliminate dead registers before splitting. v2: Add a comment written by Iago. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Drop unnecessary switch statement in nir_setup_outputs()Kenneth Graunke2016-10-241-12/+3
| | | | | | | | | | TCS and FS are skipped above. CS has no output variables. All remaining cases take the same path. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965/gen8: Don't enable alpha test and alpha to coverage if draw bufer zero ↵Anuj Phogat2016-10-241-6/+9
| | | | | | | | | | is integer type We follow this rule at multiple places in i965 driver. This patch doesn't fix any testcase. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen8: Use DrawBuffer->_IntegerBuffers in gen8_upload_ps_blend()Anuj Phogat2016-10-241-5/+2
| | | | | | | No functional changes in this patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen8: Use DrawBuffer->_IntegerBuffers in gen8_upload_blend_state()Anuj Phogat2016-10-241-8/+2
| | | | | | | No functional changes in this patch. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cs: Don't use a thread channel ID for small local sizesJordan Justen2016-10-191-2/+11
| | | | | | | | | | | | | | | | | When the local group size is 8 or less, we will execute the program at most 1 time. Therefore, the local channel ID will always be 0. By using a constant 0 in this case we can prevent using push constant data. This is not expected to be common a occurance in real applications, but it has been seen in tests. We could extend this optimization to 16 and 32 for SIMD16 and SIMD32, but it gets a bit more complicated, because this optimization is currently being done early on, before we have decided the SIMD size. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/cs: Use udiv/umod for local IDsJordan Justen2016-10-191-1/+1
| | | | | | | This allows for more optimizations relating to power-of-two divisions. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: remove gl_shader_compiler_options::EmitNoNoiseMarek Olšák2016-10-192-2/+0
| | | | | | | it's always true Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: fix subnr overflow in suboffset()Iago Toral Quiroga2016-10-191-8/+5
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Fix gl_InvocationID in dual object GS where invocations == 1.Kenneth Graunke2016-10-171-1/+4
| | | | | | | | | | | | | | | | | | | | dEQP-GLES31.functional.geometry_shading.instanced.geometry_1_invocations draws using a geometry shader that specifies layout(points, invocations = 1) in; and then uses gl_InvocationID. According to the Haswell PRM, the "GS Instance ID 0" (and 1) thread payload fields are undefined in dual object mode: "If 'dispatch mode' is DUAL_OBJECT this field is not valid." But there's no point in using them - if there's only one invocation, the ID will be 0. So just load a constant. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Silence unused parameter warningsIan Romanick2016-10-177-9/+5
| | | | | | | | | | | | | | | | | | | | brw_link.cpp:76:44: warning: unused parameter ‘shader_type’ [-Wunused-parameter] gl_shader_stage shader_type, ^ brw_nir.c: In function ‘brw_nir_lower_vs_inputs’: brw_nir.c:194:55: warning: unused parameter ‘devinfo’ [-Wunused-parameter] const struct gen_device_info *devinfo, ^ brw_vec4_visitor.cpp:914:37: warning: unused parameter ‘sampler’ [-Wunused-parameter] uint32_t sampler, ^ brw_vec4_visitor.cpp:1146:34: warning: unused parameter ‘stream_id’ [-Wunused-parameter] vec4_visitor::gs_emit_vertex(int stream_id) ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Enable OpenGL 4.5.Kenneth Graunke2016-10-142-2/+2
| | | | | | | | | Everything is in place. There are still conformance issues to sort out, but we may as well turn it on in master. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* intel/blorp: Add a flag to make blorp not re-emit dept/stencil buffersJason Ekstrand2016-10-141-6/+6
| | | | | | | | | | | In Vulkan, we want to be able to use blorp to perform clears inside of a render pass. If blorp stomps the depth/stencil buffers packets then we'll have to re-emit them. This gets tricky when secondary command buffers get involved. Instead, we'll simply guarantee that the depth and stencil buffers we pass to blorp (if any) match those already set in the hardware. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i915: workaround multiple intelFenceExtension definitionsEmil Velikov2016-10-141-0/+1
| | | | | | | | | | | | | Due to conflicting symbol names (between i915 and i965) in the megadriver, we use a set of defines in i915/intel_screen.h. With a recent commit we've introduced a symbol intelFenceExtension which has different implementation for each driver, yet we forgot to add the define. Fixes: d11515ff1b3 ("i915/sync: Implement DRI2_Fence extension") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98264 Signed-off-by: Emil Velikov <[email protected]>
* i965: Sort some extension namesIan Romanick2016-10-141-3/+3
| | | | | | | Trivial. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i915: store reference to the context within struct intel_fence (v2)Mauro Rossi2016-10-141-11/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Porting of the corresponding patch for i965. Here follows the original commit message by Tomasz Figa: "As the spec allows for {server,client}_wait_sync to be called without currently bound context, while our implementation requires context pointer. v2: Add a mutex and acquire it for the duration of brw_fence_client_wait() and brw_fence_is_completed() as suggested by Chad." NOTE: in i915 all references to 'brw' are replaced by 'intel' Marshmallow-x86 boots ok with the following results of Android CTS. Android CTS 6.0_r7 build:2906653 Session Pass Fail Not Executed 0(EGL) 1410 24 0 1(GLES2) 13832 82 0 I get the same results as per i965GM. [Emil Velikov: Include Mauro's test results] Signed-off-by: Emil Velikov <[email protected]>
* i915/sync: Implement DRI2_Fence extensionMauro Rossi2016-10-143-30/+152
| | | | | | | | | | | Here is the porting of corresponding patch for i965, i.e. commit c636284 i965/sync: Implement DRI2_Fence extension Here follows part of original commit message by Chad Versace: "This enables EGL_KHR_fence_sync and EGL_KHR_wait_sync." Signed-off-by: Emil Velikov <[email protected]>
* i915/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync'Mauro Rossi2016-10-142-26/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | This is the porting of corresponding patch for i965, i.e. commit 2516d83 i965/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync' The only difference compared to i965 one is that intel_check_sync() was renamed to intel_gl_check_sync() here, as it is more appropriate. Here follows original commit message by Chad Versace: "I'm about to implement DRI2_Fenc in intel_syncobj.c. To prevent madness, we need to prefix functions for GL_ARB_sync with 'gl' and functions for DRI2_Fence with 'dri'. Otherwise, the file will become a jumble of similiarly named functions. For example: old-name: intel_client_wait_sync() new-name: intel_gl_client_wait_sync() soon-to-come: intel_dri_client_wait_sync() I wrote this renaming commit separately from the commit that implements DRI2_Fence because I wanted the latter diff to be reviewable." [Emil Velikov: rename the outstanding intel_sync instances] Signed-off-by: Emil Velikov <[email protected]>
* mesa: remove 'params' parameter from ctx->Driver.TexParameter()Brian Paul2016-10-133-6/+5
| | | | | | | | | | | None of the drivers which implement this hook do anything with the texture parameter value. Drivers just look at the pname and set a dirty flag if needed. We were doing some ugly casting and type conversion to setup the argument so that all goes away. Reviewed-by: Marek Olšák <[email protected]>
* i965: solve cubemap negative x/y/z faces buffer offset issue in dEQP.Xu,Randy2016-10-111-1/+3
| | | | | | | | | | | | | | Add the miptree level/slice x/y_offset when count the surface offset in brw_emit_surface_state. The surface offset has two parts, one is from mt->offset, which should be 32 aligned in width/height for tiled buffer; another is from mt->level[current_level].slice[current_slice]. x/y_offset. This fix will solve 12 deqp failure dEQP-EGL.functional.image.create.gles2_cubemap_negative_*_texture Signed-off-by: Xu,Randy <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: remove remaining tabs in brw_draw.cTimothy Arceri2016-10-061-13/+13
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: get inputs read from nir infoTimothy Arceri2016-10-0610-20/+39
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: get outputs written from nir infoTimothy Arceri2016-10-066-22/+34
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: get outputs read from nir infoTimothy Arceri2016-10-062-2/+3
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: remove remaining tabs in brw_wm.cTimothy Arceri2016-10-061-44/+44
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: get uses discard from nir infoTimothy Arceri2016-10-061-2/+4
| | | | | | | | | | This is a step towards dropping the GLSL IR version of do_set_program_inouts() in i965 and moving towards native nir support. This is important because we want to eventually convert to nir and use its optimisations passes before we can call this GLSL IR pass. Reviewed-by: Kenneth Graunke <[email protected]>
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