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* Fix invalid extern "C" around header inclusion.Mark Janes2015-03-058-18/+8
| | | | | | | | | | | System headers may contain C++ declarations, which cannot be given C linkage. For this reason, include statements should never occur inside extern "C". This patch moves the C linkage statements to enclose only the declarations within a single header. Reviewed-by: Jose Fonseca <[email protected]>
* i965: Tell intel_get_memcpy() which direction the memcpy() is going.Matt Turner2015-03-055-42/+106
| | | | | | | | | | | | | | | | | | | | | | The SSSE3 swizzling code was written for fast uploads to the GPU and assumed the destination was always 16-byte aligned. When we began using this code for fast downloads as well we didn't do anything to account for the fact that the destination pointer given by glReadPixels() or glGetTexImage() is not guaranteed to be suitably aligned. With SSSE3 enabled (at compile-time), some applications would crash when an SSE aligned-store instruction tried to store to an unaligned destination (or an assertion that the destination is aligned would trigger). To remedy this, tell intel_get_memcpy() whether we're uploading or downloading so that it can select whether to assume the destination or source is aligned, respectively. Cc: 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89416 Tested-by: Uriy Zhuravlev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* xmlpool: make sure we ship options.hEmil Velikov2015-03-051-1/+1
| | | | | | | | | | | | The header is included in ../xmlpool.h. With the latter of which used directly in a number of places in mesa. Note that we can also add it (alongside t_option.h) to noinst_HEADERS, but neither solution fixes the issue that brough us here - namely: Do not regenerate the headers, if it already exists. Cc: "10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* swrast: include stdio.h where neededBrian Paul2015-03-051-0/+1
| | | | | Acked-by: Matt Turner <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* nouveau: include stdio.h where neededBrian Paul2015-03-053-0/+3
| | | | | Acked-by: Matt Turner <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* dri/common: include stdio.h where neededBrian Paul2015-03-052-0/+2
| | | | | Acked-by: Matt Turner <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* i965/fs: Don't propagate cmod to inst with different type.Matt Turner2015-03-042-0/+38
| | | | | | Cc: 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89317 Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix uint64_t overflow in intel_client_wait_sync()Kristian Høgsberg2015-03-041-0/+8
| | | | | | | | | | | | DRM_IOCTL_I915_GEM_WAIT takes an int64_t for the timeout value but GL_ARB_sync takes an uint64_t. Further, the ioctl used to wait indefinitely when passed a negative timeout, but it's been broken and now returns immediately in that case. Thus, if an application passes UINT64_MAX to wait forever, we overflow to -1LL and return immediately. Work around this mess by clamping the wait timeout to INT64_MAX. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel: fix EGLImage renderbuffer _BaseFormatFrank Henigman2015-03-032-3/+2
| | | | | | | | | | Correctly set _BaseFormat field when creating a gl_renderbuffer with EGLImage storage. Change-Id: I8c9f7302d18b617f54fa68304d8ffee087ed8a77 Signed-off-by: Frank Henigman <[email protected]> Reviewed-by: Stéphane Marchesin <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Fix assertion in brw_reg_type_lettersBen Widawsky2015-03-021-1/+1
| | | | | | | | | | | | | | | | | While using various debugging features (optimization debug, instruction dumping, etc) this function is called in order to get a readable letter for the type of unit. On GEN8, two new units were added, the Qword and the Unsigned Qword (Q, and UQ respectively). The existing assertion tries to determine that the argument passed in is within the correct boundary, however, it was using UQ as the upper limit instead of Q. To my knowledge you can only hit this case with the branch I am currently working on, so it doesn't fix any known issues. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Rename some PIPE_CONTROL flagsBen Widawsky2015-03-025-14/+14
| | | | | | | | | | | | | | I'm not really sure of the origins of the existing flag names. Modern docs have some slightly different names. Having the correct names makes it easier to determine if existing PIPE_CONTROL flag settings are correct, as well as making adding new PIPE_CONTROLs easier. This originally came up while I was trying to implement workarounds and spotted some things called, "flush" which should have been called "invalidate." Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Don't use backend_visitor::instructions after creating the CFG.Matt Turner2015-03-021-10/+0
| | | | | | | | | | | | | | | | | | | | This is a fix for a regression introduced in commit a9f8296d ("i965/fs: Preserve the CFG in a few more places."). The errata this code works around is described in a comment before the function: "[DevBW, DevCL] Errata: A destination register from a send can not be used as a destination register until after it has been sourced by an instruction with a different destination register. The framebuffer write's sources must be in message registers, which SEND instructions cannot have as a destination. There's no way for this errata to affect anything at the end of the program. Just remove the code. Cc: 10.4, 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84613 Reviewed-by: Kenneth Graunke <[email protected]>
* i915: Remove hand-rolled memcpy implementation.Matt Turner2015-03-022-29/+1
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove hand-rolled memcpy implementation.Matt Turner2015-03-022-28/+1
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965: Consider scratch writes to have side effects.Matt Turner2015-03-021-0/+1
| | | | | | | | We could do better by tracking scratch reads and writes. Cc: 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88793 Reviewed-by: Jason Ekstrand <[email protected]>
* radeon: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-10/+10
| | | | Acked-by: Ilia Mirkin <[email protected]>
* r200: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-10/+10
| | | | Acked-by: Ilia Mirkin <[email protected]>
* nouveau: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-4/+4
| | | | Acked-by: Ilia Mirkin <[email protected]>
* i965: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-025-8/+8
| | | | Acked-by: Ilia Mirkin <[email protected]>
* i915: replace Elements() with ARRAY_SIZE()Brian Paul2015-03-021-1/+1
| | | | Acked-by: Ilia Mirkin <[email protected]>
* i965: Remove the create_raw_surface vtbl hook.Francisco Jerez2015-03-025-47/+8
| | | | | | | | It's a wrapper around emit_buffer_surface_state with format=RAW, pitch=1, rw=true and the remaining arguments ordered differently. There's no point in having a separate vtbl pointer for that. Reviewed-by: Kristian Høgsberg <[email protected]>
* i965: Add missing defines for render cache messages.Francisco Jerez2015-03-022-2/+8
| | | | | | And remove duplicated definition of OWORD_DUAL_BLOCK_WRITE. Reviewed-by: Paul Berry <[email protected]>
* i965/skl: Lay out a 1D miptree horizontallyNeil Roberts2015-03-021-2/+60
| | | | | | | On Gen9+ the 1D miptree is laid out with all of the mipmap levels in a horizontal line. Reviewed-by: Ben Widawsky <[email protected]>
* i965/skl: Lay out 3D textures the same as array texturesNeil Roberts2015-03-021-2/+8
| | | | | | | On Gen9+ the 3D textures use the same mipmap layout as 2D array textures. Reviewed-by: Ben Widawsky <[email protected]>
* i965/skl: Fix the maximum thread count format for the PSNeil Roberts2015-03-021-1/+6
| | | | | | | According to the bspec for some reason the format of the maximum number of threads field has changed from U8-2 to U8-1 for the PS. Reviewed-by: Anuj Phogat <[email protected]>
* i965/gs: Check newly-generated GS-out VUE map against correct stageChris Forbes2015-03-011-1/+1
| | | | | | | | | | | | | | | Previously, we compared our new GS-out VUE map to the existing *VS*-out VUE map, which is bogus. This would mostly manifest as redundant dirty flagging where the GS is in use but the VS and GS output layouts differ; but there is a scary case where we would fail to flag a GS-out layout change if it happened to match the VS-out layout. Signed-off-by: Chris Forbes <[email protected]> Cc: "10.5, 10.4" <[email protected]> Reviewed-by: Matt Turner <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88885
* i965: add GLSL_TYPE_DOUBLE switch case to silence warningBrian Paul2015-02-281-0/+1
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/fs/nir: Mark fallthrough.Matt Turner2015-02-281-0/+1
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* i965/fs/nir: Mark fallthrough.Matt Turner2015-02-281-0/+1
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* i965: Avoid applying negate to wrong MAD source.Matt Turner2015-02-272-30/+26
| | | | | | | | | | | | For some given GLSL IR like (+ (neg x) (* 1.2 x)), the try_emit_mad function would see that one of the +'s sources was a negate expression and set mul_negate = true without confirming that it was actually a multiply. Cc: 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89315 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89095 Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4: Fix implementation of i2b.Matt Turner2015-02-271-1/+1
| | | | | | | | I broke this in commit 2881b123d. I must have misread i2b as b2i. Cc: 10.5 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88246 Reviewed-by: Ian Romanick <[email protected]>
* i965/fs/nir: Use emit_math for nir_op_fpowIan Romanick2015-02-271-1/+1
| | | | | | | | | It appears that all the other instructions that need it already use it. This one just got missed. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Cc: "10.5" <[email protected]>
* i965: Fix I/L/LA SNORM formats.Kenneth Graunke2015-02-271-1/+19
| | | | | | | | | | | | | | | _mesa_choose_tex_format (texformat.c) tries I8_SNORM, L8_SNORM, and either L8A8_SNORM or A8L8_SNORM, none of which are supported by our driver. Failing that, it falls back to RGBX for luminance, and RGBA intensity and luminance alpha. So, we need to use swizzle overrrides to obtain the correct values. Fixes Piglit's EXT_texture_snorm/fbo-blending-formats and fbo-clear-formats. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Patch the instruction generating discards; don't use CMP.Z.Kenneth Graunke2015-02-271-2/+3
| | | | | | | | | | | | | | | | | | | CMP.Z doesn't work on Gen4-5 because the boolean isn't guaranteed to be 0 or 0xFFFFFFFF - only the low bit is defined. We can call emit_bool_to_cond_code to generate the condition in f0.0; the last instruction will generate the flag value. We can patch it to use f0.1, and negate the condition. Fixes discard tests on Gen4-5. Haswell shader-db stats: total instructions in shared programs: 5770279 -> 5769112 (-0.02%) instructions in affected programs: 64342 -> 63175 (-1.81%) helped: 1069 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Introduce brw_negate_cmod().Kenneth Graunke2015-02-272-0/+23
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* swrast: replace INLINE with inlineBrian Paul2015-02-262-6/+6
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeon: replace INLINE with inlineBrian Paul2015-02-265-8/+8
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r200: replace INLINE with inlineBrian Paul2015-02-263-4/+4
| | | | Reviewed-by: Alex Deucher <[email protected]>
* i915: replace INLINE with inlineBrian Paul2015-02-2610-22/+22
| | | | Reviewed-by: Alex Deucher <[email protected]>
* mesa: don't include math.h in compiler.hBrian Paul2015-02-261-0/+1
| | | | | | | | Not needed by anything in that header. Include math.h or c99_math.h where needed instead. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* mesa: include stdarg.h only where it's usedBrian Paul2015-02-261-0/+1
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRTAnuj Phogat2015-02-251-0/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Pass pointer to miptree as function parameter in ↵Anuj Phogat2015-02-251-6/+6
| | | | | | | | | intel_horizontal_texture_alignment_unit This will be used by next patch in the series. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Allocate texture buffer in intelTexImageAnuj Phogat2015-02-251-2/+11
| | | | | | | | | before calling _mesa_meta_pbo_TexSubImage(). This will be used in later patches and will be required in Skylake to get the tile resource mode of miptree before calling _mesa_meta_pbo_TexSubImage(). Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Make a function to check the conditions to use the blitterAnuj Phogat2015-02-251-11/+29
| | | | | | | No functional changes in the patch. Just makes the code look cleaner. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Move the comment to the right placeAnuj Phogat2015-02-251-1/+1
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Fix condition to use Y tiling in blitter in intel_miptree_create()Anuj Phogat2015-02-251-3/+3
| | | | | | | Y tiling is supported in blitter on SNB+. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* i965: Don't force x-tiling for 16-bpp formats on Gen>7Neil Roberts2015-02-251-3/+3
| | | | | | | | | | | | Sandybridge doesn't support y-tiling for surface formats with 16 or more bpp. There was previously an override to explicitly allow this for Gen7. However, this restriction is also removed in Gen8+ so we should use y-tiling there too. This is important to do for Skylake which doesn't support x-tiling for 3D surfaces. Reviewed-by: Ben Widawsky <[email protected]>
* dri/common: Update comment about driQueryRendererIntegerCommonAndreas Boll2015-02-251-0/+1
| | | | | | | | | Since 87d3ae0b45b6b6bb50b583dafa55eb109449a005 driQueryRendererIntegerCommon handles __DRI2_RENDERER_PREFFERED_PROFILE too. Signed-off-by: Andreas Boll <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Remove redundant discard jumps.Kenneth Graunke2015-02-242-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | With the previous optimization in place, some shaders wind up with multiple discard jumps in a row, or jumps directly to the next instruction. We can remove those. Without NIR on Haswell: total instructions in shared programs: 5777258 -> 5775872 (-0.02%) instructions in affected programs: 20312 -> 18926 (-6.82%) helped: 716 With NIR on Haswell: total instructions in shared programs: 5773163 -> 5771785 (-0.02%) instructions in affected programs: 21040 -> 19662 (-6.55%) helped: 717 v2: Use the CFG rather than the old instructions list. Presumably the placeholder halt will be in the last basic block. v3: Make sure placeholder_halt->prev isn't the head sentinel (caught twice by Eric Anholt). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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