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* i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-09-041-0/+11
| | | | | | | See comment on Vertex URB Entry Read Length for VS_STATE. This, combined with the previous three commits, fixes #22945. (cherry picked from commit e340d4f9866db4bae391288e83a630a310b0dd2b)
* i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt2009-09-041-1/+8
| | | | | | | This fix is just from code and docs inspection, but it may fix hangs on some applications. (cherry picked from commit e93848e595176ae0bad3bfe64e0ca63fd089bb72)
* i965: Don't emit bad packets when no VBs are referenced.Eric Anholt2009-09-041-0/+22
| | | | | | | | | | It appears that sometimes Mesa (and I suppose a VS could as well) emits a program which references no vertex data, and thus we end up with nr_enabled == 0 even though some VBs are enabled. We'd end up emitting VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs. Bug #22945 (wine with an uncompiled VS) (cherry picked from commit d1fbfd0f962347e4153db3852292d44de5aea863)
* i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt2009-09-042-29/+18
| | | | | The code duplication bothered me. (cherry picked from commit 9b9cb30d128fc5f1ba77287696ecd508e640efde)
* i965: Set the max index buffer address correctly according to the docs.Eric Anholt2009-09-041-1/+1
| | | | | It's the last addressable byte, not the byte after the end of the buffer. (cherry picked from commit b72dea5441e8e9226dabf1826fa3bc129c7bc281)
* i965: rename var: s/tmp/vs_inputs/Brian Paul2009-09-041-8/+8
| | | | (cherry picked from commit 840c09fc71542fdfc71edd2a2802925d467567bb)
* dri: Fix problems with unitialized values in dri screen object.Pauli Nieminen2009-08-071-1/+1
| | | | | | This fixes crash in r200 KMS driver when pSAREA was set to 1 randomly because of memory wasn't cleared. Signed-off-by: Pauli Nieminen <[email protected]>
* intel: Fix inverted test for disabling flushing of front buffer output.Brian Paul2009-08-041-1/+1
| | | | | | | | | | The comment disagreed with the code, and nicely drew my eyes to what was going wrong. Bug #21774 (blender) Bug #21788 (readpix) (cherry picked from master, commit fd65418f600874b05f902b622078b40bc1abb24a)
* intel: Wait on the last swapbuffers to complete before queuing a new one.Brian Paul2009-08-043-0/+28
| | | | | | | | | | | | | This fixes jerkiness in doom3 and other apps since the kernel change to throttle less absurdly, which led to a thundering herd of frames. Because this is a rather minimal fix, there is at least one downside: If the whole scene completes in one batchbuffer, we'll end up stalling the GPU. Thanks to Michel Dänzer for suggesting using glFlush to signal frame end instead of going to all the effort of adding a new DRI2 extension. (cherry picked from master, commit 0828579a658af01a64b5e699175dc9bbbedcd685)
* intel: Fix leak of DRI option info due to using the wrong free routine.Brian Paul2009-07-271-1/+1
| | | | (cherry picked from commit 6d66f23c50ebe8f973757b6fd1b81c9b7920c447)
* intel: Clean up leak of driver context structure on context destroy.Brian Paul2009-07-271-0/+3
| | | | (cherry picked from commit ddef7dc87b2001fbe117ee5f24a0c645ee95a03c)
* intel: Use _mesa_warning() to report GEM warningsBrian Paul2009-07-271-3/+3
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* intel: Fall back on glBitmap with fog enabled.Eric Anholt2009-07-201-0/+6
| | | | | | | | We would have to build the program with the appropriate fog mode, and also supply the fog coordinate if appropriate. Bug #19413. (cherry picked from commit 8ae02a3919bf31bd33f86208472e100eedb58497)
* i965: Don't clip everything if FRONT_AND_BACK culling while culling disabled.Eric Anholt2009-07-201-1/+2
| | | | | | | Fixes everything-black with meta_clear_tris on quake4-mpdemo and doom3-demo. Bug #18844, 22077. (cherry picked from commit 81d555068408d4343d7627c8bedda5675f09bd21)
* radeon: With DRI1, if we have HW stencil, only expose fbconfigs with stencil.Michel Dänzer2009-07-201-2/+2
| | | | | | | | | | | | Otherwise simple apps like glxgears pick up a DirectColor visual since the X server mixes the depth 32 visual in with the other GLX visuals, and this seems to result in a (mostly) black screen due to a bad ColorMap for a lot of people. The bad ColorMap may be a bug in the apps, the X server or X driver, and regardless of that I think the X server should ideally make the depth 32 GLX visual separate from the rest again, but in the meantime this makes us cope. (depth_bits is either 16 or 24, never 0)
* r128: fix two-sided lighting segfault seen in GLUT's olight demoPeteri Andras2009-07-133-2/+7
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* intel: Bump driver data, add RC3 tagintel_2009q2_rc3Ian Romanick2009-07-121-1/+1
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* i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger2009-07-044-17/+16
| | | | | | | | | | | | the driver used to overwrite grf0 then use implicit move by send instruction to move contents of grf0 to mrf1. However, we must not overwrite grf0 since it's still used later for fb write. Instead, do the move directly do mrf1 (we could use implicit move from another grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't seem to make sense). I think the dp_READ/WRITE_16 functions may suffer from the same issue. While here also remove unnecessary msg_reg_nr parameter from the dataport functions since always message register 1 is used.
* i965: Remove bad constant buffer constant-reg-already-loaded optimization.Eric Anholt2009-07-041-13/+11
| | | | | | | Thanks to branching, the state of c->current_const[i].index at the point of emitting constant loads for this instruction may not match the actual constant currently loaded in the reg at runtime. Fixes a regression in my GLSL program for idr's class since b58b3a786aa38dcc9d72144c2cc691151e46e3d5.
* intel: Also update stencil bits in intel_update_wrapper().Michel Dänzer2009-07-031-0/+1
| | | | | Fixes assertion failure when binding depth/stencil texture to FBO stencil attachment.
* i915: Fix assertion failure on remapping a non-BO-backed VBO.Eric Anholt2009-06-301-1/+4
| | | | | | Failure to set the obj->Pointer back to null tripped up the assertion. Bug #22428. (cherry picked from commit 57a06d3a48c9af1067ec05e3ad96c58f4b9b99be)
* intel: added null ptr checkBrian Paul2009-06-291-1/+1
| | | | This fixes a segfault seen with piglit's fdo20701 test.
* intel / DRI2: Additional flush of fake front-buffer to real front-bufferIan Romanick2009-06-261-0/+11
| | | | | | | | | | | To maintain correctness, the server will copy the real front-buffer to a newly allocated fake front-buffer in DRI2GetBuffersWithFormat. However, if the DRI2GetBuffersWithFormat is triggered by glViewport, this will copy stale data into the new buffer. Fix this by flushing the current fake front-buffer to the real front-buffer in intel_viewport. Fixes bug #22288.
* i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger2009-06-221-0/+1
| | | | | | | glsl compiler will not generate OPCODE_SWZ, and as a first step it would be translated away to a MOV anyway (why?), but later internally this opcode is generated (for EXT_texture_swizzling). (cherry picked from commit 4ef1f8e3b52a06fcf58f78c9c36738531b91dbac)
* intel: intel_texture_drawpixels() can't handle GL_DEPTH_STENCIL.Michel Dänzer2009-06-221-1/+1
| | | | | Fixes glean depthStencil test. (cherry picked from commit 3885b708fdbb7bbd5dd3a247c41fb9a75ee7c057)
* i965: added intelFlush() call in intel_get_tex_image()Brian Paul2009-06-221-0/+6
| | | | | Fixes the render-to-texture test in progs/tests/getteximage.c (cherry picked from commit a03b349153660e449daf4f56d750f1caef23b1a5)
* intel: Fix other metaops versus GL_COMPILE_AND_EXECUTE dlists.Eric Anholt2009-06-192-3/+3
| | | | | | Fixes oglconform zbfunc.c and pxtrans-cidraw.c, at least. (cherry picked from commit 405300bb190f516e16b704050abe3389b366ed27)
* intel: Fix glClear behavior versus display lists.Eric Anholt2009-06-191-1/+1
| | | | | | | The CALL_DrawArrays was leaking the clear's primitives into the display list with GL_COMPILE_AND_EXECUTE. Use _mesa_DrawArrays instead, which doesn't appear to leak. Fixes piglit dlist-clear test. (cherry picked from commit 64edde1004f7a69e77877bba24d315a92bcd47c8)
* radeons: use dp4 for position invariant vertex programsRoland Scheidegger2009-06-193-0/+6
| | | | | | | | Fixes #22181. R200 requires this since DP4 is used in hw tnl mode. R300 prefers it (should be faster due to no instruction dependencies), but both methods should be correct (when sw tcl is used though, MUL/MAD might be faster). Probably doesn't make much difference for R100 since vertex progs are executed in software anyway, but let's just keep it the same there too.
* intel: remove extra \n from warning stringBrian Paul2009-06-171-1/+1
| | | | (cherry picked from commit 42e9bde0fa2276b8f5bb434328eea7665794b127)
* i965: fix 1D texture borders with GL_CLAMP_TO_BORDERRobert Ellison2009-06-171-0/+10
| | | | | | | | | | | | | | | With 1D textures, GL_TEXTURE_WRAP_T should be ignored (only GL_TEXTURE_WRAP_S should be respected). But the i965 hardware seems to follow the value of GL_TEXTURE_WRAP_T even when sampling 1D textures. This fix forces GL_TEXTURE_WRAP_T to be GL_REPEAT whenever 1D textures are used; this allows the texture to be sampled correctly, avoiding "imaginary" border elements in the T direction. This bug was demonstrated in the Piglit tex1d-2dborder test. With this fix, that test passes. (cherry picked from commit ab6c4fa582972e25f8800c77b5dd5b3a83afc996)
* i965: send all warnings through _mesa_warning()Robert Ellison2009-06-171-1/+1
| | | | | | | | | | | | One warning message: drm_i915_getparam: -22 was still being sent to fprintf(). This causes all Piglit tests to fail, even with MESA_DEBUG=0. Using _mesa_warning() to emit the message allows the general Mesa controls for messages like this to be applied. (cherry picked from commit bc3270e99f5c39544aaf831742db14796ab83a6a)
* i965: fix segfault on low memory conditionsRobert Ellison2009-06-171-0/+7
| | | | | | | | When out of memory (in at least one case, triggered by a longrunning memory leak), this code will segfault and crash. By checking for the out-of-memory condition, the system can continue, and will report the out-of-memory error later, a much preferable outcome. (cherry picked from commit 44a4abfd4f8695809eaec07df8eeb191d6e017d7)
* i915: Don't put VBOs in graphics memory unless required for an operation.Eric Anholt2009-06-172-1/+40
| | | | | | This saves doing swtnl from uncached memory, which is painful. Improves clutter test-text performance by 10% since it started using VBOs. (cherry picked from commit a945e203d4fe254593bc0c5c5d6caca45e65f9f7)
* i915: Fall back on NPOT textured metaops on 830-class.Eric Anholt2009-06-173-0/+30
| | | | (cherry picked from commit 8ec6e036792decf5149a209e51cb5e93ccc5c754)
* i915: Restore the Viewport and DepthRange functions on 8xx.Eric Anholt2009-06-171-0/+21
| | | | | | | | Fixes failed viewport updates on glxgears (and other apps) resize since e41780fedc2c1f22b43118da30a0103fa68b769f. Bug #20473. (cherry picked from commit 0e83e8f51af07a3066519f169f07d9afbf23252e)
* i956: Make state dependency of SF on drawbuffer bounds match Mesa's.Eric Anholt2009-06-171-2/+5
| | | | | | | Noticed while debugging a weird 1D FBO testcase that left its existing viewport and projection matrix in place when switching drawbuffers. Didn't fix the testcase, though. (cherry picked from commit 3a521d84ecc646fcc65fa3fe7c5f1fdbdebe8bc2)
* intel: Don't complain on falling back from PBO fastpaths.Eric Anholt2009-06-171-3/+3
| | | | | | | Instead, stash the debug info under the handy debug flag. Bug #20053 (cherry picked from commit 22690482e692cb5ed2f84d3e69545c09292e3484)
* i915: Use Stencil.Enabled instead of Stencil._Enabled in DrawBuffers.Eric Anholt2009-06-171-1/+1
| | | | | | | | | The _Enabled field isn't updated at the point that DrawBuffers is called, and the Driver.Enable() function does the testing for stencil buffer presence anyway. bug #21608 for Radeon (cherry picked from commit 4c6f82989983eecc0b3b724716cb3bcb675664c5)
* i915: Only use the new 945 cube layout for compressed textures.Eric Anholt2009-06-171-1/+4
| | | | | | | | | | The docs actually explain this, but not in a terribly clear manner. This nearly fixes the piglit cubemap testcase, except that something's going wrong with the nearest filtering at 2x2 sizes in the testcase. Looks good by visual inspection, though. Bug #21692 (cherry picked from commit 5c5a46884899ea25cdf25545d6ab3d9a74eafa3a)
* i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt2009-06-171-8/+10
| | | | | I don't have a testcase for this, but it seems clearly wrong. (cherry picked from commit dc657f3929fbe03275b3fae4ef84f02e74b51114)
* i965: Fix register allocation of GLSL fp inputs.Eric Anholt2009-06-174-13/+27
| | | | | | | | | | | Before, if the VP output something that is in the attributes coming into the WM but which isn't used by the WM, then WM would end up reading subsequent varyings from the wrong places. This was visible with a GLSL demo using gl_PointSize in the VS and a varying in the WM, as point size is in the VUE but not used by the WM. There is now a regression test in piglit, glsl-unused-varying. (cherry picked from commit 0f5113deed91611ecdda6596542530b1849bb161)
* intel: Use FRONT_AND_BACK for StencilOp as well.Eric Anholt2009-06-171-1/+2
| | | | (cherry picked from commit 64980125c76b05501a6fe7fe20fe52438f459129)
* intel: Use GL_FRONT_AND_BACK for stencil clearing.Eric Anholt2009-06-171-1/+2
| | | | | | This comes from a radeon-rewrite fallback fix, but may also fix stencil clear failure when the polygon winding mode is flipped. (cherry picked from commit d866abeffc7e4a29736fa35fb8ac09c3a28a44d6)
* intel: Skip the DRI2 renderbuffer update when doing Viewport on an FBO.Eric Anholt2009-06-171-1/+1
| | | | (cherry picked from commit d4a42b0ce6455d03be70aa56aacd779be193aca4)
* intel: Map write-only buffer objects through the GTT when possible.Eric Anholt2009-06-172-2/+15
| | | | | | This looks to be a win of a few percent in cairogears with new vbo code, thanks to not polluting caches. (cherry picked from commit aa422b262509bc0763a50f63a51a1730139ea52f)
* GLX: attempt to fix glean makeCurrent test cases.Brian Paul2009-06-171-1/+5
| | | | | | | | | | | | | Two parts to this: One we don't keep pointers to possibly freed memory anymore once we unbind the drawables from the context. Brian I need to figure out what the comment you made there, can we get a glean/piglit test so we can fix it properly? If the new gc is the same as the oldGC, we call the unbind even though we just bound it in that function. doh. (cherry picked from master, commit 77506dac8e81e9548a7e9680ce367175fe5747af)
* i965: fix bugs in projective texture coordinatesBrian Paul2009-06-165-20/+54
| | | | | | | | | | | | | | | | | | | | | | | | For the TXP instruction we check if the texcoord is really a 4-component atttibute which requires the divide by W step. This check involved the projtex_mask field. However, the projtex_mask field was being miscalculated because of some confusion between vertex program outputs and fragment program inputs. 1. Rework the size_masks calculation so we correctly set bits corresponding to fragment program input attributes. 2. Rename projtex_mask to proj_attrib_mask since we're interested in more than just texcoords (generic varying vars too). 3. Simply the indexing of the size_masks and proj_attrib_mask fields. 4. The tracker::active[] array was mis-dimensioned. Use MAX_PROGRAM_TEMPS instead of a magic number. 5. Update comments, add new assertions. With these changes the Lightsmark demo/benchmark renders correctly, until we eventually hit a GPU lockup...
* intel: Release fb backing regions in intelDestroyBuffer()Shuang He2009-06-151-0/+24
| | | | Fixes memory leak when destroying framebuffers.
* intel: Clip to window after calling Driver.TexImage2DIan Romanick2009-06-021-9/+8
| | | | | | | | | | This prevents the width / height from being clipped to the window size before the texture is allocated. This matches intelCopyTexImage1D. This should fix bug #21227 Signed-off-by: Ian Romanick <[email protected]> (cherry picked from commit 129f311673c99eb912d659023e50bc5f0ef53249)
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