| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | r300: Merged the Vector and Math Engine opcode macros. | Oliver McFadden | 2008-03-24 | 3 | -153/+225 | |
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| | * | r300: Corrected a bug with the SUB instruction. | Oliver McFadden | 2008-03-02 | 1 | -0/+16 | |
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| | * | r300: Corrected a bug with the MAD instruction. | Oliver McFadden | 2008-03-02 | 2 | -4/+12 | |
| | | | | | | | | | | | The PVS_VECTOR_OPCODE macro should be modified to support macro instructions, too. | |||||
| | * | r300: Added the PVS_SRC_OPERAND documentation from AMD. | Oliver McFadden | 2008-03-01 | 2 | -38/+56 | |
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| | * | r300: Added the PVS_OP_DST_OPERAND documentation from AMD. | Oliver McFadden | 2008-03-01 | 2 | -22/+56 | |
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| | * | r300: Added a TODO comment for registers missing from AMD's documentation. | Oliver McFadden | 2008-03-01 | 1 | -0/+2 | |
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| | * | r300: Moved the vertex program shift/mask defines into the appropriate file. | Oliver McFadden | 2008-03-01 | 2 | -27/+23 | |
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| | * | r300: Indented the vertex program code with longer lines. | Oliver McFadden | 2008-03-01 | 1 | -462/+304 | |
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| | * | r300: Moved the PREFER_DP4 define near the position invariant function. | Oliver McFadden | 2008-03-01 | 1 | -3/+3 | |
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| | * | r300: Added a TODO comment for the MAD opcodes. | Oliver McFadden | 2008-03-01 | 1 | -0/+4 | |
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| | * | r300: Use the VE_ADD hardware opcode for the SUB opcode. | Oliver McFadden | 2008-03-01 | 1 | -19/+1 | |
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| | * | r300: Use the VE_MULTIPLY hardware opcode for the MUL opcode. | Oliver McFadden | 2008-03-01 | 1 | -1/+1 | |
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| | * | r300: Cleaned up the XPD opcode temporary register usage. | Oliver McFadden | 2008-03-01 | 1 | -2/+3 | |
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| | * | r300: Cleaned up extra white space. | Oliver McFadden | 2008-03-01 | 1 | -33/+0 | |
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| | * | r300: Prefer to use the VE_ADD for simple MOV style opcodes. | Oliver McFadden | 2008-03-01 | 1 | -30/+0 | |
| | | | | | | | | | | | The VE_MULTIPLY_ADD has further restrictions on reading temporary memory which may complicate things. See AMD's documentation. | |||||
| | * | r300: Removed the (undocumented) MAD_2 opcode. | Oliver McFadden | 2008-03-01 | 2 | -64/+6 | |
| | | | | | | | | | | | | | This opcode is likely a mistake from reverse engineering. MAD_2 isn't included in AMD's documentation, and my testing reviles there is no problem using the documented MAD opcode. | |||||
| | * | r300: Cleaned up the MAD/MAD_2 opcode selection. | Oliver McFadden | 2008-03-01 | 1 | -25/+36 | |
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| | * | r300: Renamed some misleading macro arguments. | Oliver McFadden | 2008-03-01 | 1 | -15/+15 | |
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| | * | r300: Cleaned up the vertex program macros. | Oliver McFadden | 2008-03-01 | 1 | -33/+24 | |
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| | * | r300: Removed duplicate component selection defines. | Oliver McFadden | 2008-03-01 | 3 | -42/+22 | |
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| | * | r300: Removed duplicate source register class defines. | Oliver McFadden | 2008-03-01 | 3 | -17/+12 | |
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| | * | r300: Renamed the vertex program source register macro. | Oliver McFadden | 2008-03-01 | 3 | -30/+30 | |
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| | * | r300: Removed the (obsolete) special source register macros. | Oliver McFadden | 2008-03-01 | 2 | -43/+24 | |
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| | * | r300: Cleaned up the special vertex program source register macros. | Oliver McFadden | 2008-03-01 | 1 | -9/+18 | |
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| | * | r300: Added the vertex program swizzle (aka selection) defines. | Oliver McFadden | 2008-03-01 | 2 | -24/+21 | |
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| | * | r300: Converted to the new src/dest register defines. | Oliver McFadden | 2008-03-01 | 3 | -24/+4 | |
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| | * | r300: Removed an obsolete comment from the vertex program header file. | Oliver McFadden | 2008-03-01 | 1 | -4/+0 | |
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| | * | r300: Converted to the new Math Engine defines. | Oliver McFadden | 2008-03-01 | 2 | -22/+9 | |
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| | * | r300: Added the Math Engine opcode macro. | Oliver McFadden | 2008-03-01 | 1 | -0/+9 | |
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| | * | r300: Renamed the Vector Engine opcode macro. | Oliver McFadden | 2008-03-01 | 3 | -40/+40 | |
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| | * | r300: Converted to the new Vector Engine defines. | Oliver McFadden | 2008-03-01 | 4 | -76/+32 | |
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| | * | r300: Removed the duplicate dest register defines. | Oliver McFadden | 2008-03-01 | 3 | -12/+8 | |
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| | * | r300: Removed the duplicate "easy" vertex program macros. | Oliver McFadden | 2008-03-01 | 2 | -21/+19 | |
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| | * | r300: Added the vertex program src/dest register defines. | Oliver McFadden | 2008-03-01 | 1 | -0/+16 | |
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| | * | r300: Added the Vector Engine and Math Engine defines from AMD's documentation. | Oliver McFadden | 2008-03-01 | 1 | -2/+84 | |
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| | * | r300: Moved the vertex and fragment program macros into the appropriate files. | Oliver McFadden | 2008-03-01 | 4 | -151/+121 | |
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| * | | i965: depth offset on glPolygonMode(GL_LINE/GL_POINT) | Xiang, Haihao | 2008-03-28 | 1 | -2/+2 | |
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| * | | r300: finish conversion of RS_INST regs | Dave Airlie | 2008-03-28 | 3 | -22/+6 | |
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| * | | r300: move to using RS_INST names | Dave Airlie | 2008-03-28 | 5 | -37/+33 | |
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| * | | [965] Fix massively broken state cache dirty flagging. | Michal Wajdeczko | 2008-03-26 | 1 | -2/+6 | |
| | | | | | | | | | | | It was flagging a last_bo update even when last_bo didn't change, but another part was failing to update last_bo when it should have. | |||||
| * | | [intel] Use mesa texmemory functions to allocate teximage Data. | Michal Wajdeczko | 2008-03-26 | 2 | -3/+5 | |
| | | | | | | | | | | | Failure to consistently do so resulted in mismatched aligned versus unaligned alloc/free. | |||||
| * | | [965] Don't let the negate flags of src0 affect 1 constants in precalc_dst/lit | Eric Anholt | 2008-03-26 | 1 | -14/+21 | |
| | | | | | | | | | | | This patch is a variant of a submission by Michal Wajdeczko to fix oglconform fpalu failures. | |||||
| * | | [965] Correctly set read mask for OPCODE_SWZ in pass1. | Michal Wajdeczko | 2008-03-26 | 1 | -1/+1 | |
| | | | | | | | | | | | | | While OPCODE_SWZ has usually been optimized away in pass0, it may still exist if a SWZ with dst saturate was emitted in pass_fp. Fixes an error in oglconform fpalu.c. | |||||
| * | | [965] Clean up whitespace and dead code from do_unfilled change. | Eric Anholt | 2008-03-26 | 1 | -11/+6 | |
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| * | | [i915] don't use 4x4 filter for 1D shadowmap | Zou Nan hai | 2008-03-26 | 1 | -2/+7 | |
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| * | | intel: fix the issue "VBO: Cannot allocate memory for a BO" on | Xiang, Haihao | 2008-03-25 | 3 | -0/+14 | |
| | | | | | | | | | 965 after merging intel_context.c from i915 and i965. fix bug# 15152. | |||||
| * | | R300: fix typo r300 fog reg | Alex Deucher | 2008-03-24 | 1 | -1/+1 | |
| | | | | | | | | | Noticed by pzad on IRC | |||||
| * | | [965] Avoid emitting dead code for DPx/math instructions. | Michal Wajdeczko | 2008-03-21 | 1 | -0/+15 | |
| | | | | | | | | | | | | | The pass1 optimization stage clears out writemasks and registers, but the instructions themselves are still being processed at this stage, and could have resulted in them still being emitted. | |||||
| * | | [965] Improve pinterp performance by delaying reads of just-written regs. | Michal Wajdeczko | 2008-03-21 | 1 | -0/+4 | |
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| * | | [965] Fix negating of unsigned value in emit_wpos_xy. | Michal Wajdeczko | 2008-03-21 | 1 | -1/+1 | |
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