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* intel: Enable EXT_gpu_program_parameters.Eric Anholt2009-06-291-0/+2
* Merge branch 'mesa_7_5_branch'Brian Paul2009-06-291-1/+1
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| * intel: added null ptr checkBrian Paul2009-06-291-1/+1
* | Revert "intel: Remove unneded pthread mutex in LOCK_HARDWARE."Eric Anholt2009-06-291-1/+8
* | intel: Move note_unlock() implementation to the one place it's needed.Eric Anholt2009-06-296-26/+2
* | intel: Remove unneded pthread mutex in LOCK_HARDWARE.Eric Anholt2009-06-291-6/+0
* | intel: Make LOCK_HARDWARE recursive to avoid hand-rolling recursiveness.Eric Anholt2009-06-295-47/+19
* | Revert "r200: make use of DMA buffers for Elts a lot better."Dave Airlie2009-06-293-19/+16
* | radeon: Always initialize front and back renderbuffers if presentNicolai Hähnle2009-06-271-2/+1
* | radeon: Update .gitignoreNicolai Hähnle2009-06-272-2/+25
* | Merge branch 'arb_vertex_array_object'Brian Paul2009-06-262-19/+47
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| * | intel: enable GL_ARB_vertex_array_object extensionBrian Paul2009-06-221-0/+2
| * | mesa: regenerated files related to GL_ARB_vertex_array_objectBrian Paul2009-06-191-19/+45
* | | Merge branch 'mesa_7_5_branch'Brian Paul2009-06-261-0/+11
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| * | intel / DRI2: Additional flush of fake front-buffer to real front-bufferIan Romanick2009-06-261-0/+11
* | | i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger2009-06-264-17/+16
* | | r200: make use of DMA buffers for Elts a lot better.Dave Airlie2009-06-263-16/+19
* | | r200: only emit unitneeded texturesDave Airlie2009-06-261-0/+2
* | | radeon: fix hw texture limitsRoland Scheidegger2009-06-253-9/+14
* | | radeon/r200: add some hw texture limitsDave Airlie2009-06-252-2/+8
* | | radeon: fix stupidity in cs space check code.Dave Airlie2009-06-251-2/+6
* | | intel: fix additional merge conflicts missed in previous commitBrian Paul2009-06-242-18/+0
* | | Merge branch 'mesa_7_5_branch'Brian Paul2009-06-243-0/+21
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| * | i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger2009-06-221-0/+1
| * | intel: intel_texture_drawpixels() can't handle GL_DEPTH_STENCIL.Michel Dänzer2009-06-221-1/+1
| * | i965: added intelFlush() call in intel_get_tex_image()Brian Paul2009-06-221-0/+6
| * | intel: Fix other metaops versus GL_COMPILE_AND_EXECUTE dlists.Eric Anholt2009-06-192-3/+3
| * | intel: Fix glClear behavior versus display lists.Eric Anholt2009-06-191-1/+1
| * | radeons: use dp4 for position invariant vertex programsRoland Scheidegger2009-06-193-0/+6
| * | intel: remove extra \n from warning stringBrian Paul2009-06-171-1/+1
| * | i965: fix 1D texture borders with GL_CLAMP_TO_BORDERRobert Ellison2009-06-171-0/+10
| * | i965: send all warnings through _mesa_warning()Robert Ellison2009-06-171-1/+1
| * | i965: fix segfault on low memory conditionsRobert Ellison2009-06-171-0/+7
| * | i915: Don't put VBOs in graphics memory unless required for an operation.Eric Anholt2009-06-172-1/+40
| * | i915: Fall back on NPOT textured metaops on 830-class.Eric Anholt2009-06-173-0/+30
| * | i915: Restore the Viewport and DepthRange functions on 8xx.Eric Anholt2009-06-171-0/+21
| * | i956: Make state dependency of SF on drawbuffer bounds match Mesa's.Eric Anholt2009-06-171-2/+5
| * | intel: Don't complain on falling back from PBO fastpaths.Eric Anholt2009-06-171-3/+3
| * | i915: Use Stencil.Enabled instead of Stencil._Enabled in DrawBuffers.Eric Anholt2009-06-171-1/+1
| * | i915: Only use the new 945 cube layout for compressed textures.Eric Anholt2009-06-171-1/+4
| * | i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt2009-06-171-8/+10
| * | i965: Fix register allocation of GLSL fp inputs.Eric Anholt2009-06-174-13/+27
| * | intel: Use FRONT_AND_BACK for StencilOp as well.Eric Anholt2009-06-171-1/+2
| * | intel: Use GL_FRONT_AND_BACK for stencil clearing.Eric Anholt2009-06-171-1/+2
| * | intel: Skip the DRI2 renderbuffer update when doing Viewport on an FBO.Eric Anholt2009-06-171-1/+1
| * | intel: Map write-only buffer objects through the GTT when possible.Eric Anholt2009-06-172-2/+15
| * | GLX: attempt to fix glean makeCurrent test cases.Brian Paul2009-06-171-1/+5
* | | i965: Disable texture tiling by default.Eric Anholt2009-06-231-5/+1
* | | i965: Set the max index buffer address correctly according to the docs.Eric Anholt2009-06-231-1/+1
* | | i965: Don't set a reserved bit in MI_FLUSH.Eric Anholt2009-06-231-1/+1
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