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| | * | | Test for TTM presence initially rather than test for lack of classic aperture.Eric Anholt2007-06-182-10/+23
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| | * | | Replace intel_dump_batchbuffer with a more informational version.Eric Anholt2007-06-153-22/+619
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| | * | | Correct a mis-count in a LOAD_STATE_IMMEDIATE_1 length argument.Eric Anholt2007-06-151-1/+1
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| * | | | Add buffer manager destroy function.Eric Anholt2007-05-315-3/+30
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| * | | | Remove some stale comments.Eric Anholt2007-05-311-2/+0
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| * | | Replace the flags/hint arguments to bo_alloc{,_static} with a location mask.Eric Anholt2007-05-247-44/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, allocations only take locations, rather than a variety of unused flags. The only interesting flag before was the no_move/no_evict pair for scanout and similar buffers, which the DRI drivers don't use. That will be readded when we get to using this code for display buffer allocation, by adding a pin/unpin call (dynamic pinning/unpinning may be useful for VT switching and root window resizing). This commit changes one instance of DRM_BO_FLAG_MEM_LOCAL with DRM_BO_FLAG_MEM_TT, which appeared to have been unintentional.
| * | | Merge branch 'master' into i915-unificationEric Anholt2007-05-2445-674/+458
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/i915tex/i830_texstate.c src/mesa/drivers/dri/i915tex/i915_texstate.c
| * | | | Don't read beyond the end of the buffer with INTEL_DEBUG=bat.Eric Anholt2007-05-211-5/+15
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| * | | | Enable INTEL_DEBUG environment variable.Eric Anholt2007-05-211-1/+1
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| * | | | Remove unused intel_batchpool.c.Eric Anholt2007-05-211-418/+0
| | | | | | | | | | | | | | | | | | | | | | | | | This may need to be implemented again, but probably not as a buffer manager (pool).
| * | | | Notify the fake buffer manager on contended lock take.Eric Anholt2007-05-212-0/+11
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| * | | | Merge branch 'master' into i915-unificationEric Anholt2007-05-1891-6622/+5700
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/common/dri_bufmgr.c src/mesa/drivers/dri/common/dri_drmpool.c src/mesa/drivers/dri/i915tex/intel_batchpool.c src/mesa/drivers/dri/i915tex/intel_buffer_objects.c src/mesa/drivers/dri/i915tex/intel_regions.c src/mesa/drivers/dri/i915tex/intel_screen.c src/mesa/drivers/dri/i915tex/intel_screen.h
| * | | | | Fix a refcounting mistake with first_swap_fence.Eric Anholt2007-05-181-1/+1
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| * | | | | Fix another mis-calling of _fence_wait_internal.Eric Anholt2007-05-181-1/+1
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| * | | | | Allow unreference with a NULL argument.Eric Anholt2007-05-181-0/+6
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| * | | | | Fix double-counting of low_offset in block->virtual.Eric Anholt2007-05-181-1/+2
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| * | | | | Zero out bufmgr_fake on alloc.Eric Anholt2007-05-181-1/+1
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| * | | | | Dead code elimination and fix bufmgr_fake_wait_idle.Eric Anholt2007-05-181-4/+1
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| * | | | | Kill old struct bufmgr members.Eric Anholt2007-05-182-6/+0
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| * | | | | Fix some use-before-initialize in bufmgr_fake.Eric Anholt2007-05-181-0/+5
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| * | | | | Ratchet required version down to 1.5 (pre-TTM).Eric Anholt2007-05-181-1/+1
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| * | | | | Restore missing intel_batchbuffer_reset() which was needed.Eric Anholt2007-05-171-4/+16
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| * | | | | Rename the i915tex_dri.so driver to just i915_dri.so again.Eric Anholt2007-05-171-1/+1
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| * | | | | Convert i915tex to the new interface and make it compile.Eric Anholt2007-05-1730-803/+320
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| * | | | | WIP: Replace TTM buffer pool manager with a simplified interface.Eric Anholt2007-05-167-797/+1455
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interface is not solid yet (some simplification to do still, and adjustment for 0-copy), and the drivers are not converted. However, the new interface allows using the same calls to support either a TTM or a classic static allocation backend, with the static backend allowing a more limited feature set.
* | | | | | i965: fix an error in brw_vs_tnl.cXiang, Haihao2007-09-201-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | if the state of TEXMAT is changed, the VS isn't updated.
* | | | | | nouveau: add GeForce 7300 SE to card listDave Airlie2007-09-201-0/+1
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* | | | | | nouveau : nv1x use OUT_RING_CACHE_FORCE for ↵Matthieu Castet2007-09-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NV10_TCL_PRIMITIVE_3D_PROJECTION_MATRIX as strange results appear when the matrix is partialy updated.
* | | | | | nouveau : add OUT_RING_CACHE_FORCE* to add stuff in the cache even if the ↵Matthieu Castet2007-09-191-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | value didn't change
* | | | | | nouveau : add GL_FOG_COLOR + fix a compil errorMatthieu Castet2007-09-191-3/+14
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* | | | | Replace i915tex batchbuffer printout with a pretty-printed version.Eric Anholt2007-09-194-15/+865
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* | | | | Enable building the debug (env INTEL_DEBUG=list) code by default.Eric Anholt2007-09-191-1/+1
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* | | | | i915: Quiet valgrind by initializing the seq value the kernel writes into.Eric Anholt2007-09-191-0/+9
| | | | | | | | | | | | | | | | | | | | Also, add a couple of comments to the wait/emit IRQ functions.
* | | | | nouveau: nv10: color logic op only for nv11+Patrice Mandin2007-09-191-2/+8
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* | | | | nouveau : avoid vertex_size / 4 for each vertex opsMatthieu Castet2007-09-161-13/+12
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* | | | | nouveau : use GLfloat instead of uint32_t. After all, our vertex attributes ↵Matthieu Castet2007-09-161-10/+10
| | | | | | | | | | | | | | | | | | | | are float.
* | | | | nouveau : implement nv10_render_pointsMatthieu Castet2007-09-161-1/+28
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* | | | | nouveau : fix nv10_render functionsMatthieu Castet2007-09-161-37/+15
| | | | | | | | | | | | | | | | | | | | | | | | | use _tnl_RenderClipped helper functions that will call the right driver callback clean nv10_render_generic_primitive_elts to match nv10_render style
* | | | | nouveau : opps I introduce a bug when cleaning vertex pos attribute swap patchMatthieu Castet2007-09-161-2/+2
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* | | | | nouveau : nv1x pos vertex attribute need to be the first in mesa.Matthieu Castet2007-09-161-14/+58
| | | | | | | | | | | | | | | | | | | | Swap it latter in order it match hw format.
* | | | | nouveau : use new nouveau_reg.h with correct Bracket in macroMatthieu Castet2007-09-155-370/+3863
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* | | | | nouveau : check for nmesa->state_cache.atoms overflowMatthieu Castet2007-09-141-0/+1
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* | | | | nouveau : fix NV10_TCL_PRIMITIVE_3D_CLIP_PLANEMatthieu Castet2007-09-142-3/+3
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* | | | | i965: align the address of the first element withinXiang, Haihao2007-09-141-0/+22
| | | | | | | | | | | | | | | | | | | | the index buffer. (fix#11910)
* | | | | nouveau : diable broken light enable on nv10Matthieu Castet2007-09-131-1/+11
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* | | | | Remove unused plane->pipe mapping fields from SAREA private.Jesse Barnes2007-09-122-6/+0
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* | | | | DESTDIR support.Dan Nicholson2007-09-121-2/+2
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* | | | | i965: translate shadow compare function into correctXiang, Haihao2007-09-123-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | internal function to match the EXT_shadow_funs spec. fix bug#11925
* | | | | i965: revert commit 1a15b2169ba6cb100627eb525a20a00537cfb6f0,Xiang, Haihao2007-09-122-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and keep the instruction state unchanged after calling brw_emit_tri_setup/brw_emit_line_setup when building setup thread for SF_UNFILLED_TRIS.
* | | | | Fix-up #includes to remove some -I options.Brian2007-09-1114-50/+48
| | | | | | | | | | | | | | | | | | | | eg: #include "shader/program.h" and remove -I$(TOP)/src/mesa/program