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* i965: remove UseProgram driver callbackBrian Paul2010-06-101-10/+0
* intel: Remove unnecessary header.Vinson Lee2010-06-101-1/+0
* i965: Add support for GL_ALPHA framebuffer objects.Eric Anholt2010-06-106-14/+85
* intel: Use the blitter to upload TexSubImage data to busy textures.Eric Anholt2010-06-091-10/+67
* i965: Avoid calloc/free in the CURBE upload process.Eric Anholt2010-06-095-20/+26
* intel: Flag NEW_BUFFERS when changing draw buffers.Eric Anholt2010-06-081-0/+1
* intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.Eric Anholt2010-06-089-60/+41
* intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.Eric Anholt2010-06-0844-272/+277
* intel: Clean up stale comments in intel_batchbuffer.c.Eric Anholt2010-06-081-4/+1
* intel: Remove the non-gem paths for batchbuffer upload.Eric Anholt2010-06-081-22/+4
* intel: Update comment in intel_tex_copy from before miptree x/y rework.Eric Anholt2010-06-081-1/+1
* r600: Make next_inst() static.Henri Verbeet2010-06-082-59/+61
* r600: Assert output registers have a valid export index.Henri Verbeet2010-06-081-0/+4
* r600: Process exports for all written fragment outputs.Henri Verbeet2010-06-081-26/+12
* r600: Fill uiFP_OutputMap for all written fragment outputs.Henri Verbeet2010-06-081-16/+17
* r300compiler: fix scons buildJoakim Sindholt2010-06-051-0/+2
* i915: Only emit a MI_FLUSH when the drawing rectangle offset changes.Chris Wilson2010-06-052-8/+24
* i915: Fix off-by-one for drawing rectangle.Chris Wilson2010-06-051-2/+2
* i915: Inhibit render cache flush when changing drawing rectangle offset.Chris Wilson2010-06-051-1/+1
* r300/compiler: implement SIN+COS+SCS for vertex shadersMarek Olšák2010-06-053-21/+76
* r300/compiler: implement SNE unwound for r3xx VS, natively for r5xx VSMarek Olšák2010-06-052-1/+37
* r300/compiler: implement SEQ unwound for r3xx VS, natively for r5xx VSMarek Olšák2010-06-052-0/+36
* r300/compiler: implement SFL for vertex shadersMarek Olšák2010-06-051-2/+3
* i915: Don't use XRGB8888 on 830 and 845.Eric Anholt2010-06-043-2/+18
* i915: Clamp minimum lod to maximum texture level too.Eric Anholt2010-06-041-1/+3
* intel: Fix intel_compressed_num_bytes for FXT1 after I broke it.Eric Anholt2010-06-041-1/+1
* r300/compiler: print opcode names instead of numbersMarek Olšák2010-06-033-8/+8
* dri/swrast: Remove unnecessary header.Vinson Lee2010-06-021-1/+0
* intel: Remove a leftover DRI1/DRI2 conditionalKristian Høgsberg2010-06-021-7/+2
* intel: Fallback to meta if we're asked to CopyTexImage2D from RGB to RGBAKristian Høgsberg2010-06-011-0/+8
* swrast: add TFP support to swrast.Dave Airlie2010-05-311-0/+69
* gallium: fix TFP on galliumDave Airlie2010-05-311-0/+1
* intel: Initialize batch->reserved_space on allocationChris Wilson2010-05-311-2/+1
* r300: fix blits for textures of width/height greater than 2048 on r5xxMarek Olšák2010-05-291-5/+9
* i965: Add cache unit -> bo name mapping for more gen6 state objects.Eric Anholt2010-05-281-0/+3
* i965: fix PIPE_CONTROL command for gen6.Zou Nan hai2010-05-281-1/+10
* Enable hardware mipmap generation for radeon.Will Dyson2010-05-261-3/+8
* Fix image_matches_texture_obj() MaxLevel checkWill Dyson2010-05-261-4/+7
* Fallback to software render if there is no miptree for an imageWill Dyson2010-05-261-4/+4
* i965: Add support for EXT_timer_query on Ironlake.Eric Anholt2010-05-262-24/+67
* intel: Handle decode of PIPE_CONTROL instructions.Eric Anholt2010-05-261-0/+27
* i965: Move Gen6 debugging emit_mi_flush into the Gen6 block.Eric Anholt2010-05-261-2/+2
* i965: Don't PIPE_CONTROL instruction cache flush.Eric Anholt2010-05-261-1/+0
* i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.Eric Anholt2010-05-261-0/+7
* r300/compiler: implement SGT+SLE opcodesMarek Olšák2010-05-261-0/+20
* r300/compiler: fix dumping r5xx vertex shadersMarek Olšák2010-05-261-0/+3
* r300/compiler: move hardware caps to the radeon_compiler base structMarek Olšák2010-05-266-18/+19
* r300/compiler: shorten swizzle expressionsMarek Olšák2010-05-261-44/+65
* i965: Add support for all 8 possible ARB_draw_buffers in Mesa.Eric Anholt2010-05-232-2/+1
* i965: Fix bit allocation for number of color regions for ARB_draw_buffers.Eric Anholt2010-05-231-1/+1
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