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* i965/fs: Skip assertion on NaN.Matt Turner2016-01-131-1/+2
* i965/fs: Add debugging to constant combining pass.Matt Turner2016-01-131-1/+20
* i965/gen9: Don't allow the RGBX formats for texturing/renderingNeil Roberts2016-01-131-0/+28
* i965: Mark TCS URB writes as having side effects.Kenneth Graunke2016-01-121-0/+1
* meta/blit: Use internal functions for sampler object accessIan Romanick2016-01-111-2/+2
* i965: Upload 3DSTATE_BINDING_TABLE_POINTERS_HS when !TCS on Gen9+.Kenneth Graunke2016-01-111-3/+4
* Add missing platform information for KBLMark Janes2016-01-111-0/+5
* glsl: Move _mesa_shader_stage_to_string/abbrev to shader_enums.cKristian Høgsberg Kristensen2016-01-084-4/+0
* i965: Move GLSL lowering passes out of libi965_compiler.laKristian Høgsberg Kristensen2016-01-081-5/+5
* i965/compiler: Enable more lowering in NIRJason Ekstrand2016-01-071-0/+7
* i965: use _mesa_delete_buffer_objectNicolai Hähnle2016-01-071-1/+1
* i915: use _mesa_delete_buffer_objectNicolai Hähnle2016-01-071-1/+1
* radeon: use _mesa_delete_buffer_objectNicolai Hähnle2016-01-071-1/+1
* mesa: Add KBL PCI IDs and platform information.Sarah Sharp2016-01-061-0/+60
* nir: Add a lower_fdiv option, turn fdiv into fmul/frcp.Kenneth Graunke2016-01-051-0/+1
* i965: Only turn on ARB_compute_shader if we can write registers.Kenneth Graunke2016-01-051-2/+3
* i965: Use rcp in brw_lower_texture_gradients rather than 1.0 / x.Kenneth Graunke2016-01-051-1/+1
* i965/gen9: Modify the conditions to use blitter on skl+Anuj Phogat2016-01-051-3/+9
* i965/gen9: Return false in place of assert in intelEmitCopyBlit()Anuj Phogat2016-01-051-3/+4
* i965/gen9: Remove regions overlap check in fast copy blitAnuj Phogat2016-01-051-5/+0
* i965/gen9: Don't use fast copy blit in case of non power of 2 cppAnuj Phogat2016-01-051-2/+4
* i915/i965: Fix typo in perf_debug messageIan Romanick2016-01-052-2/+2
* i965: quieten compiler warning about out-of-bounds accessIlia Mirkin2016-01-051-0/+1
* i965/wm: use binding size for ubo/ssbo when automatic size is unsetIlia Mirkin2016-01-051-4/+10
* Revert "i965/wm: use proper API buffer size for the surfaces."Ilia Mirkin2016-01-052-9/+4
* i965/wm: use proper API buffer size for the surfaces.Samuel Iglesias Gonsálvez2016-01-042-4/+9
* nouveau: fix double-const qualifierIlia Mirkin2016-01-032-2/+2
* nir: extract out helper macros for running passesRob Clark2016-01-031-36/+9
* i965: Make TCS precompile use the TES primitive mode when available.Kenneth Graunke2016-01-021-1/+3
* i965: Push most TES inputs in SIMD8 mode.Kenneth Graunke2016-01-021-12/+30
* i965: Use LOAD_PAYLOAD for SIMD8 TES input loads, not MOV.Kenneth Graunke2016-01-021-1/+4
* i965: Move 3-src subnr swizzle handling into the vec4 backend.Kenneth Graunke2016-01-022-6/+18
* drirc: Disable ARB_blend_func_extended for Heaven 4.0/Valley 1.0.Kenneth Graunke2015-12-301-0/+8
* i965/gen8: Always use BRW_REGISTER_TYPE_UW for MUL on GEN8+Marta Lofstedt2015-12-302-29/+1
* i965: Reemit vertex state between indirect multi drawsKristian Høgsberg Kristensen2015-12-291-2/+22
* i965: Add support for gl_DrawIDARB and enable extensionKristian Høgsberg Kristensen2015-12-2912-5/+145
* i965: Add support for gl_BaseVertexARB and gl_BaseInstanceARBKristian Høgsberg Kristensen2015-12-2911-37/+88
* i965: Assert that SYSTEM_VALUE_VERTEX_ID gets loweredKristian Høgsberg Kristensen2015-12-291-0/+1
* i965: Enable ARB_tessellation_shader on Gen7-7.5.Kenneth Graunke2015-12-282-3/+3
* i965: Don't set interleave or complete on TCS EOT message.Kenneth Graunke2015-12-285-5/+41
* i965: Relase input URB Handles on Gen7/7.5 when TCS threads finish.Kenneth Graunke2015-12-285-1/+93
* i965: Use proper TCS barrier ID bits for Ivybridge/Baytrail.Kenneth Graunke2015-12-281-4/+6
* i965: Use proper TCS Instance ID bits for Ivybridge/Baytrail.Kenneth Graunke2015-12-281-2/+5
* i965: Port tessellation evaluation shaders to vec4 mode.Kenneth Graunke2015-12-288-2/+365
* i965: Emit a real 3DSTATE_DS on Gen7.Kenneth Graunke2015-12-281-11/+54
* i965: Emit a real 3DSTATE_HS on Gen7.Kenneth Graunke2015-12-281-11/+47
* i965: Add the TCS/TES state upload atoms to the gen7_atoms list.Kenneth Graunke2015-12-283-30/+14
* nir: Get rid of function overloadsJason Ekstrand2015-12-285-47/+48
* i965: Add tr_mode and mip tail information in surface state dumpAnuj Phogat2015-12-231-2/+5
* i965/gen8/cs: Gen8 requires 64 byte alignment for push constant dataJordan Justen2015-12-221-3/+3
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